FPGA PGL22G驱动RGB-LCD触摸屏【Verilog HDL驱动】.zip

Clock Regions-Block Scope: +--------------------------------------------------------------------------+ | (X0,Y*): (Xmin,Xmax,Ymin,Ymax) | (X1,Y*): (Xmin,Xmax,Ymin,Ymax) +--------------------------------------------------------------------------+ | (X0,Y2): (0,39,60,89) | (X1,Y2): (40,75,60,89) | (X0,Y1): (0,39,30,59) | (X1,Y1): (40,75,30,59) | (X0,Y0): (0,39,0,29) | (X1,Y0): (40,75,0,29) +--------------------------------------------------------------------------+ Clock Regions-Clock Primitives: +--------------------------------------------------------------------------------------------------------------------------------------+ | Clock Region Name | CLK PAD | PLL PAD | RCKB | IOCKGATE | IOCKDIV | CLMA | CLMS | DRM | APM +--------------------------------------------------------------------------------------------------------------------------------------+ | (X0,Y0) | 4 | 6 | 4 | 2 | 2 | 520 | 180 | 12 | 0 | (X0,Y1) | 4 | 6 | 4 | 2 | 2 | 610 | 210 | 12 | 0 | (X0,Y2) | 4 | 6 | 4 | 2 | 2 | 524 | 180 | 6 | 0 | (X1,Y0) | 4 | 6 | 4 | 2 | 2 | 450 | 150 | 6 | 10 | (X1,Y1) | 4 | 6 | 4 | 2 | 2 | 540 | 180 | 6 | 10 | (X1,Y2) | 4 | 6 | 4 | 2 | 2 | 630 | 210 | 6 | 10 +--------------------------------------------------------------------------------------------------------------------------------------+ Global Clock Buffer Constraint Details: +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Source Name | Source Pin | Source-Buffer Net | Buffer Input Pin | Buffer Name | Buffer Output Pin | Buffer-Load Net | Clock Region Of Buffer Site | Buffer Site | IO Load Clock Region | Non-IO Load Clock Region | Clock Loads | Non-Clock Loads +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | u_pll/u_pll_e1/goppll | CLKOUT0 | clk_50m | CLK | clkbufg_0/gopclkbufg | CLKOUT | ntclkbufg_0 | --- | --- | --- | --- | 20 | 0 +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ Global Clock Source Constraint Details: +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Source Name | Source Pin | Source-Load Net | Clock Region Of Source Site | Source Site | Clock Buffer Loads | Non-Clock Buffer Loads +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | u_pll/u_pll_e1/goppll | CLKOUT0 | clk_50m | (X0,Y2) | PLL_82_319 | 1 | 1 +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ Device Cell Placement Summary for Global Clock Buffer: +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Source Name | Source Pin | Source-Buffer Net | Buffer Input Pin | Buffer Name | Buffer Output Pin | Buffer-Load Net | Buffer Site | IO Load Clock Region | Non-IO Load Clock Region | Clock Loads | Non-Clock Loads +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | u_pll/u_pll_e1/goppll | CLKOUT0 | clk_50m | CLK | clkbufg_0/gopclkbufg | CLKOUT | ntclkbufg_0 | USCM_74_104 | --- | (43,67,51,62) | 20 | 0 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ Device Cell Placement Summary for Global Clock Source: +--------------------------------------------------------------------------------------------------------------------------------------------+ | Source Name | Source Pin | Source-Load Net | Source Site | Clock Buffer Loads | Non-Clock Buffer Loads +--------------------------------------------------------------------------------------------------------------------------------------------+ | u_pll/u_pll_e1/goppll | CLKOUT0 | clk_50m | PLL_82_319 | 1 | 1 +--------------------------------------------------------------------------------------------------------------------------------------------+