FPGAXC7A100T实现高速ADC-DAC驱动（VerilogHDL实现）.zip

共238个文件

vh：24个

v：23个

rst：22个

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FPGA

VerilogHDL

驱动程序

82 浏览量 2023-04-04 17:19:17 上传评论收藏 43.35MB ZIP 举报

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FPGA XC7A100T实现高速ADC-DAC驱动（Verilog HDL实现）.zip （238个子文件）

__synthesis_is_complete__ 0B

runme.bat 229B

hs_ad_da.bit 3.65MB

dds_256x8b_wave.coe 1KB

hs_ad_da_routed.dcp 1.73MB

hs_ad_da_placed.dcp 1.54MB

hs_ad_da_opt.dcp 1.25MB

ila_0.dcp 580KB

ila_0.dcp 579KB

dbg_hub.dcp 350KB

rom_256x8b.dcp 27KB

hs_ad_da.dcp 17KB

usage_statistics_webtalk.html 156KB

hw_ila_data_1.ila 61KB

vivado.jou 855B

vivado.jou 820B

vivado.jou 819B

vivado.jou 814B

ISEWrap.js 8KB

rundef.js 1KB

runme.log 103KB

runme.log 71KB

runme.log 33KB

runme.log 23KB

ip_upgrade.log 1KB

summary.log 899B

hs_ad_da.lpr 343B

hs_ad_da.ltx 4KB

debug_nets.ltx 4KB

rom_256x8b.mif 2KB

messagePromote.pb 173KB

vivado.pb 164KB

vivado.pb 53KB

place_design.pb 46KB

vivado.pb 37KB

write_bitstream.pb 36KB

opt_design.pb 19KB

route_design.pb 14KB

init_design.pb 4KB

hs_ad_da_power_summary_routed.pb 722B

ila_0_utilization_synth.pb 276B

hs_ad_da_utilization_placed.pb 276B

hs_ad_da_utilization_synth.pb 276B

rom_256x8b_utilization_synth.pb 276B

vivado.pb 149B

hs_ad_da_timing_summary_routed.pb 109B

hs_ad_da_drc_routed.pb 75B

hs_ad_da_methodology_drc_routed.pb 53B

hs_ad_da_route_status.pb 44B

hs_ad_da_drc_opted.pb 37B

hs_ad_da_bus_skew_routed.pb 30B

hs_ad_da_timing_summary_routed.rpt 378KB

hs_ad_da_methodology_drc_routed.rpt 247KB

hs_ad_da_io_placed.rpt 144KB

hs_ad_da_control_sets_placed.rpt 70KB

hs_ad_da_clock_utilization_routed.rpt 25KB

hs_ad_da_drc_routed.rpt 20KB

hs_ad_da_drc_opted.rpt 18KB

hs_ad_da_utilization_placed.rpt 10KB

hs_ad_da_power_routed.rpt 9KB

ila_0_utilization_synth.rpt 7KB

hs_ad_da_utilization_synth.rpt 7KB

rom_256x8b_utilization_synth.rpt 7KB

hs_ad_da_bus_skew_routed.rpt 881B

hs_ad_da_route_status.rpt 651B

hs_ad_da_power_routed.rpx 1.5MB

hs_ad_da_timing_summary_routed.rpx 756KB

hs_ad_da_methodology_drc_routed.rpx 435KB

hs_ad_da_drc_routed.rpx 40KB

hs_ad_da_drc_opted.rpx 35KB

hs_ad_da_bus_skew_routed.rpx 1KB

.vivado.begin.rst 229B

.route_design.begin.rst 190B

.opt_design.begin.rst 190B

.write_bitstream.begin.rst 190B

.place_design.begin.rst 190B

.init_design.begin.rst 190B

.vivado.end.rst 0B

.Vivado_Synthesis.queue.rst 0B

.vivado.end.rst 0B

共 238 条

The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended.

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