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FPGA XC7A100T实现高速双路DAC驱动（Verilog HDL实现）.zip
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2023-04-04
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FPGA XC7A100T实现高速双路DAC驱动（Verilog HDL实现）.zip （227个子文件） 
__synthesis_is_complete__ 0B __synthesis_is_complete__ 0B __synthesis_is_complete__ 0B runme.bat 229B runme.bat 229B runme.bat 229B runme.bat 229B hs_dual_da.bit 3.65MB rom_1024x10b.coe 7KB rom_1024x10b.coe 7KB hs_dual_da_routed.dcp 198KB hs_dual_da_physopt.dcp 191KB hs_dual_da_placed.dcp 188KB hs_dual_da_opt.dcp 173KB rom_1024x10b.dcp 30KB rom_1024x10b.dcp 30KB rom_1024x10b.dcp 30KB rom_1024x10b.dcp 30KB hs_dual_da.dcp 17KB clk_wiz_0.dcp 10KB clk_wiz_0.dcp 10KB clk_wiz_0.dcp 10KB clk_wiz_0.dcp 10KB clk_wiz_0.dcp 10KB
usage_statistics_webtalk.html 37KB vivado.jou 881B vivado.jou 860B vivado.jou 839B vivado.jou 834B ISEWrap.js 8KB ISEWrap.js 8KB ISEWrap.js 8KB ISEWrap.js 8KB rundef.js 1KB rundef.js 1KB rundef.js 1KB rundef.js 1KB runme.log 55KB runme.log 33KB runme.log 24KB runme.log 21KB summary.log 904B hs_dual_da.lpr 343B rom_1024x10b.mif 11KB rom_1024x10b.mif 11KB vivado.pb 53KB vivado.pb 38KB place_design.pb 36KB vivado.pb 33KB write_bitstream.pb 21KB route_design.pb 14KB opt_design.pb 14KB init_design.pb 5KB phys_opt_design.pb 2KB hs_dual_da_power_summary_routed.pb 728B clk_wiz_0_utilization_synth.pb 276B rom_1024x10b_utilization_synth.pb 276B hs_dual_da_utilization_placed.pb 276B hs_dual_da_utilization_synth.pb 276B vivado.pb 149B hs_dual_da_timing_summary_routed.pb 106B hs_dual_da_methodology_drc_routed.pb 52B hs_dual_da_route_status.pb 43B hs_dual_da_drc_routed.pb 37B hs_dual_da_drc_opted.pb 37B hs_dual_da_bus_skew_routed.pb 30B hs_dual_da_io_placed.rpt 144KB hs_dual_da_timing_summary_routed.rpt 122KB hs_dual_da_clock_utilization_routed.rpt 15KB hs_dual_da_drc_routed.rpt 12KB hs_dual_da_drc_opted.rpt 12KB hs_dual_da_utilization_placed.rpt 9KB hs_dual_da_power_routed.rpt 8KB hs_dual_da_utilization_synth.rpt 7KB rom_1024x10b_utilization_synth.rpt 7KB clk_wiz_0_utilization_synth.rpt 7KB hs_dual_da_control_sets_placed.rpt 4KB hs_dual_da_methodology_drc_routed.rpt 3KB hs_dual_da_bus_skew_routed.rpt 901B hs_dual_da_route_status.rpt 588B hs_dual_da_timing_summary_routed.rpx 106KB hs_dual_da_power_routed.rpx 34KB hs_dual_da_drc_routed.rpx 23KB hs_dual_da_drc_opted.rpx 23KB hs_dual_da_methodology_drc_routed.rpx 3KB hs_dual_da_bus_skew_routed.rpx 1KB .vivado.begin.rst 229B .vivado.begin.rst 229B .vivado.begin.rst 229B .vivado.begin.rst 229B .route_design.begin.rst 190B .opt_design.begin.rst 190B .phys_opt_design.begin.rst 190B .write_bitstream.begin.rst 190B .place_design.begin.rst 190B .init_design.begin.rst 190B .vivado.end.rst 0B .vivado.end.rst 0B .Vivado_Synthesis.queue.rst 0B .Vivado_Synthesis.queue.rst 0B共 227 条
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