数字下变频DDC VHDL语言 FPGA

library IEEE; 
use IEEE.STD_LOGIC_1164.ALL; 
use IEEE.STD_LOGIC_ARITH.ALL; 
use IEEE.STD_LOGIC_UNSIGNED.ALL; 
 
entity DDC is 
port( 
  Clk        : in std_logic; 
  Rst        : in std_logic; 
  Data_In    : in std_logic_vector(13 downto 0); 
  DDC_F      : in std_logic_vector(31 downto 0);    --=X"4A12D773"; 
  DDC_Data_I : out std_logic_vector(15 downto 0); 
  DDC_Data_Q : out std_logic_vector(15 downto 0)); 
end entity; 
 
architecture Behavioral of DDC is 
 
signal Mul_In    : std_logic_vector(13 downto 0); 
signal sin       : std_logic_vector(11 downto 0); 
signal cos       : std_logic_vector(11 downto 0); 
signal Mul_Cos   : std_logic_vector(13 downto 0); 
signal Mul_Sin   : std_logic_vector(13 downto 0); 
signal Mulout_En : std_logic; 
signal Mulout_I  : std_logic_vector(27 downto 0); 
signal Mulout_Q  : std_logic_vector(27 downto 0); 
signal En        : std_logic; 
 
component muldown 
  port( 
    aclr   : in std_logic;