1.3寸OLED屏_驱动芯片SH1106手册

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1.3寸OLED屏_驱动芯片SH1106手册,用于开发穿戴设备
Supply Power supply input: 1.65-35V 3.0-4.2V power supply pad for Power supply for charge pump circuit Supply This pin can be disconnected or connect to v when v is supplied externally Supply Ground This is a segment voltage reference pad Supply This pad should be connected to v externally This is a common voltage reference pad Supply This pad should be connected to v externally This is a segment current reference pad. A resistor should be connected between this pad and V. Set the current at 10HA This is a pad for the voltage output high level for Common sighals a capacitor should be connected between this pad and V Nc This is an internal voltage reference pad for booster circuit. Keep floating OLED panel power supply Generated by internal charge pump Connect to capacitor. It could be supplied externally Connect to charge pump capacitor C1P These pins are not used and should be disconnedted when Vpp is supplied externally C2P Connect to charge pura capacitor. C2N These pins are not used and should be disconnedted when Vpp is supplied externally 3 v0.2 This pad is the system clock input. When internal clock is enabled, this pad should be 10 Left open. The internal clock is output from this pad. When internal oscillator is disabled, this pad receives display clock signal from external clock source This is the internal clock enable pad CLS ="H. Internal oscillator circuit is enabled CLS="L": Internal oscillator circuit is disabled (requires external input When CLS="L, an external clock source must be connected to the CL pad for normal operation These are the Mpu interface mode select pads IMO 080 12C 6800 4-wire SPl3-wire SPI IMO 0 0 0 0 IM2 IM1 1 0 0 IM2 0 0 0 This pad is the chip select input. When CS="L", then the chip select becomes active and data/command yo is enabled This is a reset signal input pad. When RES is set to"L', the settings are initialized.The reset RES operation is performed by the RES signal level IS IS The uatarcommand control pad that determines whether the dat ois tare data or a command A0:the nputs at Do to D7 are freated as display data A0f'L the inputs at Do to Di are transfered to the command registers C interface, this pad serves as sAO to distinguish the different address of OLEd driver. This is a mPU interface input pad When connected to an 8080 MPU, this is active LOW. This pad connects to the 8080 MPU WR WR (R W) I snel he sitea ts n thod set s e t hi the reinw td cenf th ani niut a / henr w=“"H"∵:Read When w="L”: Write This is a mPU interface input pad When connected to an 8080 series MPU, it is active LOW. This pad is connected to the RD signal of the 8080 series MPU, and the data bus is in an output status when this signal is "L RD When connected to a 6800 series MPU, this is active HIGH. This is used as an enable clock (E) input of the 6800 series MPU hen rd=“H":Enab|e When RD=“L: Disable This is an 8-bit bj-directional data bus that connects to an 8-bit or 16-bit standard mpu data bus D0-D7 O When the serial interface is selected then do serves as the serial clock input pad (scl)and d1 SCL serves as the serial data input pad(Sl). At this time d2 to d7 are set to high impedance (SI/SDA) vO When the I C interface is selected, then DO serves as the serial clock input pad( and d1 serves as the serial data input pad(SDAl). At this time, D2 to D7 are set to high impedance v0.2 COMO. 2 60.62 o These pads are even Common signal output for OLED display COM1.3 -61,63 These pads are odd Common signal output for OLED display SEG0-131 These pads are Segment signal output for OLED display TEST1-3 Test pad, internal pull low, no connection for user. Dummy These pads are not used. Keep floating v0.2 器|叫Ⅲy:一眼Ⅲ M sH1106 ]、33330……③国-…N区区区区-1区国区园 ALK R Top vie (um) Chip boundary 5076 814 Chip height 300 yO 40 80 15 情0 Bump size COM Pad pitch 30.75 55 ump height All pads unit: um 03030 303030 24 24 ALK L 2470 A o t 2L+ ALK R 2470 348 24 24 XY Y 10 ALK L v0.2 unit 9 7scn194[外sc*「-mx COM 55 VCOM 177581295311138 SEG31 105087323 3coM522623237P18318129511395Ec3210608329[205E610109162 29 1836.81 1030.13 20sEG101-11237323 2167.62 73|coM62 213762 SEG34 SEG1 102 COM83 -329 74coM6o|213762l EG35 210sEG1031-1187323 ②21N106819-2999 coM82197c2-329 SEG36 21462 165319-29954 2212-32[144sE7sz3329[2a2sEe106-253323 57819-299.95 COME SEG10G 127312329 523192996 146sEc39 COM50 sEG4091488 sEG108133762323 1413.19 SEG41 215sEG1091337323 13 35819-299 COM46 -225 149sEG42753:38329 sEG110-13912329 30319-2995 SEG43 248.19 acoI 151sE46918329[219sEe11[11506232 9311-29984coMo2460-135132sEc4563329[ 223SEG111413723 22日 13819-29995 SEG46 630.38 z101[9[coHM4[14■s《4A6■w9 C22N 28.19-29995 SEG48 56888 20c3192395sc2z05|13sc43+-3241|z4+s:617i43xsz 222831929590 SEG51 47865329[2235E611919e7|■39 819-299 91coM246075[159 y。D2 2460 EG53 415.3 EG14-13737323 26y2-08101295仁3coM2241[104s4304383丝e1132 VDD2 G43.19 27vRE5381029951195c0M182460195[13 sc1241262323 53319299.9596 13037 3[2警sE6126111232 coMH_12310-295L98cM2216021 59 06 EG12719218739 31 coMH3191-290959coM1023762329 sEc128195262323 VSS(REF))|-31319-29 76232 s61·_ VSS -258.19 29995 762432 29[2E61302112323 E131 WCI 2136 G65 DUMMY 156739 VcL29ss2156。zsl 61536328[z4com21x82|32 G684412 M52197c TEST 12811293a512141315321[ SEGG9 222762323 TES 0702329 225762 215132369121[0s1352633|4061631329 297 sEc7223062329 44■cs34691影299%■sc5■19133294110sE EG73 261.3 COM15 yD1■40919511c1950383 181 SEG74 DD1 SEG7 182963329 SEG75 22.87 w51.91-2995 sEG81983x9[13sEc76353682320 2460 566.B1 -384.37 COM23 相四 73 VD1 676812995118 COM2 1675.88 -476.62 /85 51 啪[sEe1164313 SEG8 9 -53.1? 1905G83568329[23coM35[24045 SEG16 155288 59962329 14sEG17152213329192 OM39 WRB sEG18149138329 -2460 1116.81 2999 SEG19 450.63 EG87 -691.8 COM43 2460 59 5161295127E62014263281[195684-22324123co520-195 SEG89 61 a1841-8511se1338-384b9+-scos084124- 62 2312364129095110sEc23119633864[198sEc981487320 COM51 1391.81 31sEe2413588326 SEG92 64 141681-2991132sE625171335[200sEc938763320 SEG26 1245.38 134sEG27 161181-29995 SEG28 1133.8g 181-7995 11513 SEGy 99937 v0.2 The 8080-Parallel Interface, 6800-Parallel Interface, Serial Interface(SPl)or IC Interface can be selected by different selections of imo-2 as shown in table 1 RES 001 D7 D6 D5 D4 D3D2D1DO E CS AO RES 011D7 D6 D5 D4 D3 D2 D1 DO RD WR CS A0RES 000 Pull low SI SCL Pull low RES 00 Pull low SI SCL Pull low RES 010 Pull low SDA SCL Pull low SAO RES The parallel interface consists of 8 bi-directional data pads(D7-D0), WR(R W),RD(E), A0 and Cs. WhenWR(R W) "H, read operation from the display RAM or the status register occurs When WR(R W)="LsWrite operation to display data RAM or internal command registers occurs, depending on the status of A0 input. The RD (E)input serves as data latch signal (clock)when it is " H, provided that CS ="L"as shown in Table 2 0 0 1|6800 C AO Do to D7 In order to match the operating frequency of display RAM with that of the microprocessor, some pipeline processing are temally performed which require the insertion of a dummy read before the first actual display data read. This is shown in Figure. 1 below R/W DATA ′N n Read Preset Incremented Column address X NX N+1X N+2 X n+1 2 Data read Set address n Dummy read Data read address n address n+1 8 v0.2 The parallel interface consists of 8 bi-directional data pads(D7-DO) WR(R W), RD(E), A0 and CS. The RD(E) input serves as data read latch signal(clock)when it is"L provided that CS ="L ". Display data or status register read is controlled by Ao signal. The WR( W)input serves as data write latch signal (clock when it is"L"and provided that CS ="L" Display data or command register write is controlled by a0 as shown in Table 3 01 8080 microprocessor bus CS AO RD WR DO to D7 Similar to 6800-series interface, a dummy read is also required before the first actual display data read The SH1106 identifies the data bus signal according to AO, D(E)and WR(R W)signals 0 Reads display d Writes display data ds status wEites control data in internal register (Command) v0.2 The serial interface consists of serial clock SCL, serial data Sl, A0 and Cs. sI is shifted into an 8-bit shift register on every rising edge of SCL in the order of D7, D6,... and DO A0 is sampled on every eighth clock and the data byte in the shift register is written to the display data ram(a0=1)or command register(A0=0)in the same clock. See Figure 2 0004-wire SPI Pull Low AO SCL (Hz) Note: "-"and hz pin Must always be HIGh or LOw CS signal could always pull low in SPI-bus application s|(D1) D7 X D6 X D5 X D4 D3 D2 D1 DO D7 SCL(DO) 6 When the chip is not active, the shift registers and the counter are reset to their initial statuses Read is not possible while in serial interface mode Caution is required on the sci signal when it gomes to line-end reflections and external noise. We recommend the operation be rechecked on the actual equipment 10 v0.2

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