SH1106非常详细的编程手册，调这个液晶必用。
COM3 ID…itth∴…y (0,0) ALK L sH1106 l-…-叫③……囚囚囚國………………囚N-国…l op vlew um chip boundary 5060 814 Chip height All pads 300 vO 40 80 SEG 15 COM 15 Bump size coM36163 14凵 15 Pad pitch COM 30 SEG 30.75 55 Bump height All pads 9±2 3 Supply Power supply input: 1.65-35V VVvVV Supply Power supply output for pad option: 1.65-35V 3.0-4.2V power supply pad for Power supply for charge pump circuit Supply This pin can be disconnected or connect to v When v is supplied externally Supply Ground Supply Ground output for pad option This is a segment voltage reference pad Supply This pad should be connected to v externally This is a common voltage reference pad Supply This pad should be connected to v externally This is a segment current reference pad. A resistor should be connected between this pad and V. Sef the current at 1quA This is a pad for the voltage output high level for common sigrials. A capacitor should be connected between this pad and V This is an intermal voltage reference pad for booster circ Keep floating OLED panel power supply Generated by internal charge pump Connect to capacitor. It could be supplied externally Connect to charge pump capacitor. C These pins are not used and should be disconnedted when vpp is supplied C1P externally C2P Connect to charge pump capacitor C2N These pins are not used and should be disconnedted when Vpp is supplied externally This pad is the system clock input. When internal clock is enabled, this pad should be CL vo Left open. The internal clock is output from this pad. When internal oscillator disabled, this pad receives display clock signal from external clock source This is the internal clock enable pad ClS ="H. nternal oscillator circuit is enabled CLS I CLS="L": Internal oscillator circuit is disabled(requires external input) When CLS ="L, an external clock source must be connected to the Cl pad for normal operation These are the mpu interface mode select pads 8080 6800 4-wire SPl 3-wire SP IM1 IM1 This pad is the chip select input Wheh cs"L", then the chip select becomes active, and data/command 1/O is enabled This is a reset ignal input pad. When res is set to "L, the settings are RE initialized The reset operation is performed by the RES signal level This is the Data/Command control pad that determines whether the data bits arel data or a command AO H the inputs at do to D7 are treated as display data Ae A0="L: the inputs at do to d7 are transferred to the command registers In IC interface, this pad serves as SAo to distinguish the different address of oled driver This is a mPu interface input pad When connected to an 8080 MPU, this is active LOW. This pad connects to the 8080 MPU WR signal. The signals on the data bus are latched at the rising edge of WR the Wr (R W) When connected to a 6800 Series MPU: This is the read/write control signal input terminal When v=“H":Read When v=“L": Write 5 This is a MPU interface input pad When connected to an 8080 series MPU. it is active LOW. This pad is connected to the rd signal of the 8080 series MPu, and the sh1106 data bus is in an output status when this signal is"L RD Vhen connected to a 6800 series mpu this is active high this is used as an enable clock input of the 6800 series MPU When rd ="H: Enable When rd=“L”: Disab|e This is an 8-bit bi-directional data bus that connects to an 8-bit or 16-bit standard MPU data bus D0-D7 10When the serial interface is selected, then DO serves as the serial clock input pad (SCL) /(SCL)and D1 serves as the serial data input pad(Sl). At this time, D2 to D7 are (SI/SDA) yo set to high impedance When the I C interface is selected, then do serves as the serial clock input pad (SCL) and D1 serves as the serial data input pad(SDAI). At this time, D2 to D7 are set to high impedance COMO. 2 -60.62 THese are even Common signal output for OLED display 6163 These pads are odd Common signal output for OLED display sE0-13 o These pads are Segment signal output for OLED display TEST1 I Test pad, internal pull low, no connection for user TEST2 I Test pad. No connection for user TEST3 I Test pad. No connection for user. Dummy These pads are not used. Keep floating 6 The 8080-Parallel Interface, 6800-Parallel Interface, Serial Interface(SPI)or IC Interface can be selected by different selections of mo-2 as shown in table 1 RES 001 D6 D5 D4 D3D2D1 DO E CS A0 RES 1 D7 D6 D5 D4 D3 D2 D1 DOI RD WR CSAO 00|0 Pull low SI SCL Pull low RES 00 Pull low SI SCL Pull low RES 10 Pull low SDA SCL Pull low SAO RES The parallel interface consists of 8 bi-directional data pads(D7-D0), WR(R W), RD(E), A0 and Cs. When WR(R W) H, read operation from the display RAM or the status register occurs When WR(R W)="LsWrite operation to display data RAM or internal command registers occurs, depending on the status of A0 input. The RD (E)input serves as data latch signal (clock when it is"H, provided that cs="L"as shown in Table 0 16800 microprocessor bus CS Do to d7 In order to mateh the operating frequency of display ram with that of the microprocessor, some pipeline processing are internally performed, which require the insertion of a dummy read before the first actual display data read. This is shown in Figure. 1 below R/ DATA N N n n十 Read L「 Preset Incremented Column address N+1 N+2 BUS holder N n+1 2 Set address n Data read Dummy read Data Read address n address n+1 The parallel interface consists of 8 bi-directional data pads(D7-D0), WR (R W), RD(E), A0 and CS. The RD(E)input serves as data read latch signal(clock)when it is"L" provided that CS="L". Display data or status register read is controlled by Ao signal. The WR(R W) input serves as data write latch signal(clock) when it is"L"and provided that CS ="L" Display data or command register write is controlled by A0 as shown in Table 3 0 18080 microprocessor bus AO RD WR Do to d7 Similar to 6800-series inter face, a dummy read is also required before the first actual display data read The SH1106 identifies the data bus signal according to Ao, RD (E)and Wr(R W)signals 0 Reads display da Writes display data. 0 Reads status s control data in internal register (Command) 8 The serial interface consists of serial clock SCL, serial data Sl, AO and cs. sI is shifted into an 8-bit shift register on every rising edge of SCL in the order of D7, D6,... and do. AO is sampled on every eighth clock and the data byte in the shift register is written to the display data RAM(A0=1)or command register(A0=0)in the same clock. See Figure 2 0 0 04-Wire SPI Pull Low AO SCL S (Hz) Note: -and hz pin must always be HiGH or LoW CS signal could always pull low in SPI-bus application SI(D1)/Z/X D7 X D6 X D5 X D4 X D3 X D2 X D1 X DO X D7 SX D5/ D6 SCL(D 4 6 7 10 When the chip is not active, the shift registers and the counter are reset to their initial statuses.> Read is not possible while in serial interface mode e Caution is required on the scl signal when it comes to line-end reflections and external noise We recommend the operation be rechecked on the actual equipment 9 The 3 wire serial interface consists of serial clock SCL, serial data Sl, and cs. sI is shitted into an g-bit shift register on every rising edge of SCL in the order of DC, D7, D6,... and Do the d c bit ( first of the 9 bit) will determine the transferred data is written to the display data RaM(D C=1)or command register(D C=O) 0 03-wire SPI Pull Low Pull Low SCL S (Hz) Note: -and Hz pin Must always be HIGH or LOW CS signal could always pull low in SPI-bus application When the chip is not active, the shift registers and the counter are reset to their initial statuses Read is not possible while in serial interface mode Caution is reduired on the scL signal when it comes to-lirhe-end reflections and external noise. We recommend the operation be rechecked on the actual equipment. The SH1106 can transfer data via a standard |2C-bus and has slave mode only in communication the command or RAM data can be written into the chip and the status and Ram data can be read out of the chip 0 o C Interface Pull LOW SAO SCL SDA Note: -"and Hz pin Must always be HIGH or LOW CS signal could always pull low in I C-bus application The C-bus is for bi-directional two - ine communication between different ics or modules the two lines are a serial data line (SDA)and a serial clock line(SCL). Both lines must be connected to a positive supply via a pull-up resistor. Data transfer may be initiated only when the bus is not busy