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matlab-基于FPGA的HDB3编译码verilog实现-源码
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matlab_基于FPGA的HDB3编译码verilog实现_源码.rar （59个子文件） 
matlab_基于FPGA的HDB3编译码verilog实现_源码 matlab_基于FPGA的HDB3编译码verilog实现_源码 
vbtodbl.v 2KB hdb3.v 569B vtob.v 1KB project_1 project_1.cache wt xsim.wdf 256B project.wpc 61B project_1.srcs sim_1 new TEST.v 1KB project_1.ip_user_files 
README.txt 130B project_1.sim sim_1 behav xsim compile.bat 828B xsim.ini 40B elaborate.bat 1KB glbl.v 1KB xvlog.log 0B TEST_vlog.prj 372B simulate.log 0B elaborate.log 595B compile.log 0B webtalk.jou 861B TEST.tcl 460B .Xil Webtalk-508904-DESKTOP-VH31686 webtalk Webtalk-509360-DESKTOP-VH31686 webtalk xvlog.pb 16B webtalk_509360.backup.log 1KB webtalk_509360.backup.jou 861B TEST_behav.wdb 24KB webtalk.log 1KB xelab.pb 1KB simulate.bat 890B xsim.dir TEST_behav 
xsimk.exe 82KB xsim.rlx 783B obj xsim_1.win64.obj 3KB xsim_1.c 5KB xsim_0.win64.obj 25KB xsim.mem 4KB xsim.type 24B xsimkernel.log 215B xsim.xdbg 2KB xsim.dbg 11KB Compile_Options.txt 242B xsim.rtti 190B webtalk xsim_webtalk.tcl 4KB usage_statistics_ext_xsim.wdm 1KB .xsim_webtallk.info 64B
usage_statistics_ext_xsim.html 3KB usage_statistics_ext_xsim.xml 3KB TempBreakPointFile.txt 29B xsim.svtype 39B xsim.reloc 2KB xsimSettings.ini 1KB xsimcrash.log 0B xil_defaultlib vbtodbl.sdb 2KB hdb3_decode.sdb 2KB hdb3.sdb 2KB xil_defaultlib.rlx 748B @t@e@s@t.sdb 3KB glbl.sdb 4KB vtob.sdb 3KB stov.sdb 2KB project_1.hw project_1.lpr 290B project_1.xpr 10KB hdb3_decode.v 1003B stov.v 688B资源评论
