基于FPGA的HDB3码编码

module test_hdb3(reset_all,data_in,clk_2m,tdp,out,tdn,select_pn); input reset_all; input data_in; input clk_2m; output tdp; output tdn; output out; output select_pn; reg data_in_buff; always@(negedge reset_all or posedge clk_2m) begin if(!reset_all)