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Verilog

FPGA

UART

串口

Serial

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MICRO - UART SYNTHESIZABLE UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER

WWW.CMOSEXOD.COM

Micro-UART

Jeung Joon Lee

4/27/2001

Recommended digital logic background: medium to

advanced

1.0 Introduction

The micro-UART is a fully functional, synthesizable,

universal asynchronous receiver transmitter core. The

core is configurable and extremely compact. A typical

synthesis will consume less than 55 flops

. The

receiver and the transmitter operates independently,

and each can be selectively disabled for synthesis.

Due to its modularity and configurability and size, the

micro-UART core is ideal for system-on-chip or as

embedded processor peripherals. There is no

restriction on the highest baud rate as long as the PLD

device technology can support it.

2.0 Micro-UART IP Package

Five files comprises the micro-UART core:

uart.v

u_xmit.v

u_rec.v

baud.v

inc.h

uart.v

This is the top-level hierarchy module. All sub-modules

are instantiated here. No logic is present in this

module.

u_xmit.v

This is the asynchronous transmitter. A state-machine,

serializer and support logic comprises the main bulk of

the logic.

u_rec.v

This is the asynchronous receiver. A dual-rank

synchronizer, state-machine, deserializer and support

logic comprises the bulk of the logic.

u_baud.v

This is the baud-rate generator. An internal “baud-

clock” which is 16 times the desired baud-rate is

generated off of the external clock.

inc.h

This is the configuration file. The baud-rate, external

clock rate and the size of the data-byte are all set from

this file. The clock generated from this module feeds

the u_rec and u_baud modules.

The following table describes the default port list of the

micro-UART.

Signal Width Type Description

sys_clk 1 I main system clock

sys_rst_l 1 I main system reset

uart_clk 1 O baud-clock. 16 x baud-rate

uart_XMIT_ 1 O This is the output of the

Results using Synplify synthesis tool.

dataH asynchronous transmitter.

xmitH 1 I An active high, 1 uart_clk

pulse starts the transmit

process.

xmit_dataH 8 I This is the data to be sent

to the remote. This data is

sampled when xmitH goes

high, so does not need to

be stable.

xmit_doneH 1 O When active high, indicates

that the xmit_dataH has

been fully transmitted.

uart_REC_

dataH

1 I This is the asynchronous

input data.

rec_dataH 8 I This is the de-serialized

received from the remote.

rec_readyH 1 O When high, indicates that a

fresh data is available on

rec_dataH

3.0 Customizing the Micro-UART IP

The micro-UART can be configured through the “inc.h”

file. Currently, 3 major parameters can be configured:

WORD_LEN

This parameter specifies the number of bits in a “word”.

The minimum is 0, and maximum is 8. The default is

8. This parameter affects both the transmitter and the

receiver.

XTAL_CLK

This parameter specifies the crystal clock feeding the

sys_clk input. This is in units of Hz.

BAUD

This parameter specifies the desired baud rate of the

micro-UART. Most typical standard baud rates are:

300, 1200, 2400, 9600, 19200, etc. However, any baud

rate can be used. This parameter affects both the

receiver and the transmitter. The default is 2400

(bauds).

This parameter specifies the width of the internal

counters used to generate the appropriate baud delay.

Make sure that this value is greater than

log2(CLK_DIV). Where CLK_DIV is defined as

XTAL_CLK/(BAUD * 16 * 2). The default is 9.

4.0 UART Theory of Operation

This section illustrates the basics of a UART operation.

However, an extensive discussion on UART is beyond

the scope of this manual, and the user is encouraged

to refer to textbooks or technical manuals. Readers

familiar on this topic are encouraged to skip over to the

next section.

Figure 1 illustrates a basic UART data packet. While

no data is being transmitted, a logic 1 must be placed

in the XMIT line. A data packet is composed of 1 start

bit, which is always a logic 0, followed by a

programmable number of data bits (typically between 6

to 8), an optional parity bit, and a programmable

MICRO - UART SYNTHESIZABLE UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER

WWW.CMOSEXOD.COM

number of stop bits (typically 1). The stop bit must

always be logic 1.

Most UART uses 8bits for data, no parity and 1 stop bit.

Thus, it takes 10 bits to transmit a byte of data.

In the UART protocol, the transmitter and the receiver

do not share a clock signal. That is, a clock signal

does not emanate from one UART transmitter to the

other UART receiver

. Due to this reason, the protocol

is said to be asynchronous.

Since no common clock is shared, a known data

transfer rate (baud rate) must be agreed upon prior to

data transmission. That is, the receiving UART needs

to know the transmitting UART’s baud rate (and

conversely the transmitter needs to know the receiver’s

baud rate, if any). In almost all cases the receiving and

transmitting baud rates are the same. The transmitter

shifts out the data starting with the LSB first.

Once the baud rate has been established (prior to initial

communication), both the transmitter and the receiver’s

internal clock is set to the same frequency (though not

the same phase). The receiver “synchronizes” its

internal clock to that of the transmitter’s at the

beginning of every data packet received. This allows

the receiver to sample the data bit at the bit-cell center.

A key concept in UART design is that UART’s internal

clock runs at much faster rate than the baud rate. For

example, the popular 16450 UART controller runs its

internal clock at 16 times the baud rate. This allows

the UART receiver to sample the incoming data with

granularity of 1/16 the baud-rate period. This

“oversampling” is critical since the receiver adds about

2 clock-ticks in the input data synchronizer uncertainty.

The incoming data is not sampled directly by the

receiver, but goes through a synchronizer which

translates the clock domain from the transmitter’s to

the that of the receiver. Additionally, the greater the

granularity, the receiver has greater immunity with the

baud rate error.

The receiver detects the start bit by detecting the

transition from logic 1 to logic 0 (note that while the

data line is idle, the logic level is high). In the case of

16450 UART, once the start-bit is detected, the next

data bit’s “center” can be assured to be 24 ticks minus

2 (worse case synchronizer uncertainty) later. From

One data protocol which does share a clock line is IIC

(inter integrated chip).

then on, every next data bit center is 16 clock ticks

later. Figure 2 illustrates this point.

Once the start bit is detected, the subsequent data bits

are assembled in a de-serializer. Error condition

maybe generated if the parity/stop bits are incorrect or

missing.

4.1 Functional Description of Receiver U_REC.v

The receiver of micro-UART is composed of a control

state-machine, de-serializer, and support logic. The

main goal of the receiver is to detect the start-bit, then

de-serialize the following bit-stream, detect the stop-bit,

and make the data available to the host.

Figure 3 illustrates the functional block diagram of the

receiver. The design is minimalist, and no error

checking logic is present by default. All of these

features are to become user-enhancements.

The signal uart_clk is 16xBaud-Rate generated by

the baud rate generator u_baud.v This clock is used

to drive all of the clock within the receiver module.

The incoming data uart_dataH is fed to the dual-rank

synchronizer before feeding to de-serializer. Note that

this synchronizer is absolutely essential since the data

present on uart_dataH is synchronous to the

transmitter’s clock, and not on the receiver’s clock.

time

start bit

(logic 0)

data byte

(6 ~ 8bits)

parity bit

(optional)

stop bit

(logic 1)

D0 D1 D2 D3 D4 D5 D6 D7 PPB

Figure 1 Basic UART packet format: 1 start bit, 8 data bits, 1

parity bit, 1 stop bit.

S D0 D1 D2 D3 D4 D5 D6 D7 PPB

detect

start bit by sensing

transition from logic

1 to logic 0

sample incoming data

at the bit-cell center

sample

stop bit

Tua =T/16

1.5T - SU

= 24Tua - 2

UART receiver samples the

incoming data using x16

Baud Rate clock

T = 1/Baud Rate. Bit-cell period.

Tua = T/16. Oversampled bit-cell period.

SU = 2 Tua. Worce case synchronizer

uncertainty.

Figure 2 Data sampling points by the UART receiver.

de-serializer

State Machine

bit-cell

counter

received bit

counter

shiftH

cntr_resetH

bitCell_cntrH

countH

rstCountH

read_bitCntrH

rec_readyH

rec_dataH

uart_dataH

uart_clk

dual-rank synchronizer

rec_datH

Figure 3 Functional block-diagram of the micro-UART receiver

MICRO - UART SYNTHESIZABLE UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER

WWW.CMOSEXOD.COM

The de-serializer is a simple serial-to-parallel shit-

machine. When this signal is active high, the de-

serializer shifts the data over by 1 bit. The default shift

first.

The received bit counter is used to keep track of the

number of data bits cumulated so far. when this count

becomes the pre-set limit (word_len parameter from

inc.h), then the state-machine stops accepting more

data bits. This counter has 2 control inputs: countH

and rstCountH. When the former is active high, the

counter is advanced by 1, when the latter is active high,

the counter is cleared to 0. Note that this is a

synchronous counter. This counter is 4-bits wide by

default.

The bit cell counter is used to generate a delay in units

of uart_clk (Baud rate Period/16). This is an up-

counter controlled only by cntr_resetH. When this

signal is active high the counter is placed in reset state.

When this signal is active low, the counter is allowed to

count up by 1.

The state-machine is a simple 5 state, Mealy type

(output is function of present state and input). Figure 4

illustrates the state flow.

The state-machine ties all of the functional units

previously described. Upon system reset, the state

machine defaults to r_START state. In this state, the

state-machine looks for the start-bit. This condition is

detected by the transition of the incoming data (which

at idle is logic 1) to a logic 0. Once the start-bit is

detected, it transitions to r_CENTER state.

In r_CENTER state, the state-machine wait for ½ bit-

cell in order to find the bit-cell center. A bit-cell is 1

baud “tick” and corresponds to16 uart_clk ticks. So ½

bit-cell corresponds to 8 uart_ticks. The bit cell

counter is used to generate this delay. The reason for

waiting for 4 uart_ticks (not 8), is that the synchronizer

uncertainty adds upto 2 uart_ticks. Additionally,

counter overhead also adds upto 2 ticks. Although it is

theoretically optimum to sample the incoming data at it

cell center, the micro-UART design allows some

margin of error (due to the fact that the data is

oversampled at x16). Once the bit-cell center is found

(after having waited 4 uart_ticks), if the state of the

rec_dataH (synchronized incoming data) is still low,

then the state machine transitions to r_WAIT state. If

rec_dataH is high, then this is not a valid start bit, so

the state machine transitions back to r_START state.

A spurious noise in the UART data line can produce

this kind of effect.

The r_WAIT state simply waits for 1 baud tick (16

uart_ticks). Note that the previous state, r_CENTER,

aligned the incoming data to the center of the start-bit

bit-cell. Once 1 baud tick is waited, the incoming data

can be sampled into the de-serializer. If all

WORD_LEN bits have been sampled, then the state

machine transitions to r_STOP state, otherwise, it

transitions to r_SAMPLE state.

In r_SAMPLE state, the state of rec_dataH is sampled

into the de-serializer.

In r_STOP state, the state of rec_dataH is “sensed” to

check for logic 1. This bit is not sampled into the de-

serializer. Note that no error condition is generated

should the expected stop bit is not active high. Before

transitioning to r_START state, a status signal is

generated, rec_readyH, to indicate that a valid data is

available for reading. Notice that rec_readyH is

flopped, or piped, before being made available. This

practice reduces critical path timing constraints.

4.2 Functional Description of Receiver U_XMIT.v

The transmitter of micro-UART is composed of bit cell

counter, transmitted bit counter, a serializer and a

state machine. Like the receiver counter-part, the

design is minimalist and contains no error detecting

logic. This also is left for user enhancements.

Figure 5 illustrates the functional block diagram.

Notice the similarities with the micro-UART receiver.

The bit-cell counter and the xmitted bit counter has the

same function and implementation as those of the

receiver, only the signal names have changed slightly.

r_START

r_CENTER

r_WAIT

r_SAMPLE

r_STOP

rec_datH = 0

rec_datH = 1

rec_datH = 0

bitCell_CntrH != 4

bitCell_CntrH != 16

recd_bitCntrH =

WORD_LEN

reset

Figure 4 micro-UART receiver State Flow

serializer

State Machine

bit-cell

counter

xmitted bit

counter

load_shiftRegH

countEnaH

bitCell_cntrH

ena_bitCountH

rst_bitCountH

bitCountH

xmit_doneH

uart_xmitH

uart_clk

xmit_dataH

1'b0

1'b1

shiftEnaH

xmitDataSelH

xmitH

Figure 5 Functional block diagram of micro-UART transmitter.

评论收藏

内容反馈

zhzhzhddd

2011-12-26

恩，英文说明书，状态机注释很详细
yangshuhe33

2012-08-01

很好用，说明书很详细。系统时钟给10M的时候，波特率115200不是很精确，给个50M系统时钟就好了。
余小树

2016-06-17

文档说明很给力
xibiren

2015-08-20

对我还是有一定的参考意义的。
wy4126

2012-03-13

英文说明，代码都不错，赞一个

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hoalee

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