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SIEMENS
ERTEC
2QQP
E
nhanc
ed R
eal-
T
ime
E
the
r
net
C
on
t
rolle
r
DATA SHEET
Features
>b
Integrated
processor
ARM926EJ-S
>b
Onchip
Peripherals
.
125 I 250 MHz Core Frequency
.
DMA
Controller
.
16 KB Data-Cache
.
6 Timers
.
16 KB Instruction-Cache
.
2 Watchdogs
.
256 KB TCM-RAM
.
8 KB Boot ROM
>b
I
/
。
Interfaces
.
Little Endian
.
2 x 2 SPI Interlaces
.
4 UARTs
.
1 1
2c-1
nteri
ace
>
System
Bus
Structure
.
One
96-bit GPIO Port
.
32 Bit I 125
MHz
AHB Bus
.
1,8 I 3,3 V 1/0 Buffers
.
Multi-Layer AHB L
ite
with 7
Masters and 12 Slaves
);>
Test
I
Debug
Functi
。
nality
.
AHB
Address Range Monitoring
.
Boundary Scan
);>
Integrated
Ethernet-Phy
>b
Local
Bus
Unit
{XHIF)
.
2 Ports
.
Allows External Master
to
access
.
Supports 100Base-TX and
-FX
internal ERTEC 200P registers
.
Auto Cross Over
.
16 I 32-Bit Data Bus
.
Auto
MDIX
.
2 x 4 Paging Registers
.
Jitter free Latency
.
>
Package
>b
Mem
。
ry
Controller
{EMC)
.
400
Pin FPBGA
.
8 I 16 I 32 Bit Data Bus
.
Size 17mm x 17 mm
.
4 chip selects
.
Ball Pitch 0,8mm
.
Supports SDRAM, SAAM, Burst
Mode Flash ROM
Di
sclaimer of Liability
We
hav
e
checked
the
contents
of
th
is
manua
l
for
agreement
wi
th
the
hardw
are
and
software
descr
i
bed
. Si
nce
dev
i
at
i
ons
cannot
be
precl
u
ded
ent
i
rely
,
we
cannot
guarantee
f
ull
agreement.
However
,
the
data
in
t
hi
s
ma
n
ua
l
are
rev
i
ewed
regu
l
ar
l
y.
Necessary
correct
i
ons
are
i
nc
l
uded
in
subs
明
uent
ed
iti
ons.
Sugges
ti
ons
for
i
mprov
ement
are
welcomed.
Copyright
。
S
i
emens
AG
20
14.
All
r
ig
ht
s r
eserved
The
repro
duct
i
on,
transm
i
ss
i
on
or
use
of
this
doc
u
men
t
or
i
ts
con
t
en
ts is
not
perm
i
tted
wi
thou
t
express
wr
i
tten
author
it
y.
Offenders
w
ill
be
li
ab
le
for
damages.
All ri
ghts
,
in
clud
i
ng
r
ig
hts
created
by
paten
t
grant
or r
eg
i
strat
ion
of
a
util
it
y
model
or
design
,
are
reserved
.
All
produc
t
and
sys
t
em
nam
es
are
r
eg
i
stered
tradema
r
ks
of
the
ir
respect
i
ve
owner
and
mu
st
be
treated
as
such.
Technical
data
subject
to
change
.
A
dditio
na l
Suppo
rt
If you have questions regarding use of the described block that are not addressed in the documentation, please
contact your Siemens representative.
Please send your
w
川
tten
questions, comments, and suggestions regarding the data sheet
to
the h
otl
ine via the e-
mail address indicated above.
In
additi
on
, you can receive general informati
on,
current product information, FAQs, and downloads pertaining
to
your applicati
on on
the Inte
rn
et at:
http
://
www
.si e mens. co m/
comdec
Technical
c
。
ntacts
for
Germany
I
Worldwide
Siemens
AG
Aut
。
ma
ti
。
n
&
Drives
ComDeC
Street
address:
Wlirzburgerstr.121
90766
Furth
Federal
Republic
。
f
Germany
Technical
Contacts
f
。
r
USA
PROFI
Interface
Center:
One
Internet
Plaza
PO
Box
4991
John
s
on
City, TN 37602-4991
Phone:
Fax:
E-mail:
0911 /750-2080
0911
17
50-2100
ComDeC@siemens.c
om
Mailing
address:
P.O.
B
。
x
2355
90713
Furth
Federal
Republic
。
f
Germany
Fax
:
+1(423)-
262-
2103
Phone:
+ 1 (
423
)-
262-
2576
E-mail
:
oic
.
industrv@>siemens
.c
om
Copyr
ight© Si
emens
AG
2014.
All
ri
gh
ts
rese
r
ved.
T
echn
i
ca
l
data
subject
to
change.
2
ERTEC
200P
Data Sh
ee
t
Ve
rsion 1.1
Contents
7
『
f
?
Inonono
ng
9990034679
0
4t4t4t4t4t4t
4·
呵,-
Functional Overview
Key
Fu
nctional Units
Processor Core Subsystem (ARM926)
Processor Bus Unit
PROFIN
ET-
IP
(P
N
斗
P
)
Peripheral Interface (PER-I
F)
Pin Description
Signal Table
Signalgroup "System"
Signalgroup
“Test”
Signalgroup “PHY”
Signalgroup "JT
AG-Po
叫
S
”
Signalgroup
“
GP
I
O-Po
叫
S
”
Signalgroup “Host Interface”
Power I GND Pins
Handling
of
Unused Pins
Maximum Ratings
AC-
and
DC-Characte
ristics
1 .
1
.1
1 . 1 . 1
1
.1
.2
1
.1
.3
1
.1
.4
2
2.1
2.1
.1
2.1.2
2.1.3
2.1.4
2.1.5
2.1.6
2.2
2.3
3
nU4t
吨
d
n
/』叫/』
吨
4
Power Dissipation
DC
Operating Conditions
AC-Parameter (Timing, Constraining)
4
4
,
nJ
』
A
『
A
『Rd
33456678901223
4
ηζηζ
少』少』少』内
ζnζnJ
』
nJ
』
nJnJnJndnd
吨。
45556777789012345566
qdnJ
叫
J
叫
JnJnJnJ
呵
J
呵
J
呵
J
巧
JAU
寸
A
斗
A
斗
A
斗
A
叶
AUτAUTAUTAU
寸
EMC
Interface
SDRAM Interface
SDRAM Timing for a read access
SDRAM Timing for write access
SRAM Interface
SRAM Timing for a read access
SRAM Timing for a write access
BurstFlash Inte
rf
ace
Hos
t-lnte
向
ce
(×
HIF)
SPI
Interfaces
PNPLL
Time-Sync Interface
JTAG
盼
Interface
Trace
斗
nterface
Design Considerations
Power Sequence
ERTEC 200P Design recommendations
Design recommendations for
ER
TEC 200P
EMC
Bus
Possible ERTEC 200P EMC configurations
ERTEC 200P
EMC
recommendations
Controlling of
an
external Level-Shifter
Design Recommendations
ER
TEC 200P supply voltages pins
Design Recommendations for ERTEC 200P
P
『
o
finet
PHYS
ERTEC 200P PHY supply voltages pins
Filtering
on
ERTEC 200P PHY supply voltages
Decoupling
on
ERTEC 200P PHY supply voltages
ERTEC 200P PROFINET TX circuit
ERTEC 200P P
ROF
INET TX circuit unused pins
ERTEC 200P PROFINET FX circuit
ERTEC 200P/ Avago
QFBR
精
5978AZ
SD circuit
E
RT
EC
200P PROFINET FX circuit unused pins
Clocking
Oscillator
External clock source
PLL Power Supply
5.1
5.1.1
5.1.1.1
5.1.1.2
5.1.2
5.1.2.1
5.1.2.2
5.1.3
5.2
5.3
5.4
5.5
5.6
5.7
6
4t
叫
J
』
nJ41nζ
呵
J414lnζ
4E4
『
4p4tnζndndnJnJAUTA
斗-
hJVEUFhd4tnζnd
12222222222222223333
auaUGU£U
丘
UGU
丘
U£U£U£UPOPoauauau£U£UGU
丘
UGU
ERTEC 200P Data Sheet
Version
1.1
3 Copyri
ght©
Siemens AG 2014. All rights reserved.
Technical data subject to change.
6.4 Reset
6.4.1
Power-On Reset Behaviour
6.4.2
Strapping Pins
6.4.3 Reset Structure
6.4.
3.1
Asynchronous PowerOn-Reset
6.4.3.2
Asynchronous Hardware
-R
eset
6.4.3.3 Asynchronous JT
AG
-Reset
6.4.3.4
Asynchronous ARM926 Watchdog-Reset
6.4.3.5 Asynchronous Software-Reset for the
ERTEC
200P (without
PN-
I
P)
6.4.3.6 Asynchronous Software-Reset of the
PN
-
IP
6.4.3.7 Asynchronous Software-Reset of the ARM926EJ-S Core
6.4.3.8 Synchronous Software-Reset (PN-
IP,
PER-
IF,
Hostinte
付
ace)
6.5 GPIO Pins
6.6 Pull-Up
I
Pu
ll-Down Resistors
6.7
Debug
7 Basic Configuration
7.1
Address Map
7.2
Interrupts
7.3
OMA
Requests
7.4
Timers
7.5 GPIO
Pin
Mapping
7.6
Configuration Pins
7.7 Boot Pins
7.7.1
Start
Up
-Times
8 Thermal Specification
9 Package
lnformati
。
n
9.1 Ordering Info I Part Numbers
9.2 400-Pin SIP-FPBGA Package
9.3 Solderi
ng
Conditions
9.4 Packing Information
9.5 Ball out
10 Quality Informa
tion
10.1
Life time I
(HW)
FIT-Rate
11
Lit
erature I References
Copyri
ght©
Siemens AG 2014. All rights reserved.
Technical data subject to change.
4
48
48
49
49
50
50
50
51
51
51
51
51
53
53
54
54
54
54
54
54
54
56
56
57
58
59
59
60
61
61
62
62
62
62
ERTEC 200P Data Sheet
Version 1.1
List
of
Figures
Figure 1: ERTEC 200P Blockdiagram
Figure 2:
SDRAM
- Ti
ming
for a read access
Figure
3:
SDRAM - Timing for a write access
Figure 4: SRAM - Timing for a read access
Figure
5:
SRAM - Timing for a write access
Figure
6:
BurstFlash - Timing for a read-burst
Figure
7:
XHIF - Sequence for a read access
Figure
8:
XHIF - Sequence for a write access
Figure 9: Debug Interface
Figure 10: ARM926 Trace Interface
Figure 11: Power Sequence example
Figure 12:
EMC
Bus configurations
Figure 13:
PHY
power filtering
Figure 14:
Pl
Riter
Figure 15: PHY decoup
li
ng
Figu
「
e
16: UTP circuit
Figure 17:
UTP
circuit unused
Figure 18: F
× circuit
Figure 19:
SD
l
evel
transl
at
i
on
circuit
Figure 20:
FX
circuit unused pins
Figure 21: Oscillator
Circuit
『
y
Figure
22
Osci
ll
ato
『
Circu
i
try
Layout Example
Figure 23: Recommended for PLL Power Supply Filter
Figure 24: Power-On Reset Behaviour
Figure 25: Timing reset
Figure 26: Startup
of
the PLL
Figure 27: Single GPIO Cell
Figure 28: Package Informati
on
Figure 29: Ballout ERTEC 200P
Li
st
of
Tables
Table 1: External
Pu
ll
wiring for the JTAG-lnterface
Table 2:
Max
i
mum
Rat
ings
Table
3:
Power Dissipation
TX
mode
Table
4:
Power Di
ss
ipation
FX
mode
Table
5:
DC
Operating Conditions
Table 6:
Def
initi
on
of SDRAM commands
Table
7:
Timing for a SDRAM read access
Table
8:
Timing for a SDRAM write access
Table
9:
Timing
for
a SRAM read access
Table
10:
Timing
for
a SRAM write access
Table
11:
Timing for a
BurstFlash
『
ead-burst
Table
12:
Timing for a XHIF read access
Table
13:
Timing for a XHIF write access
Table
14:
Timing
for
a
SPI
access
Table
15:
Timing
PNPLL
Interface
Table
16:
Timing Time-Sync Interface
Table
17:
Velocity/ impedance
on
traces
Table
18:
Min
/ max trace length
Table
19:
Minimal reset duration
Table
20:
Pull-Up I Pull-Down Resistor Values
Table
21:
GPIO Port 0 Input Mappi
ng
Table
22:
GPIO Port 1 Input Mapping
Table
23:
GPIO Port 2 Input Mapping
Table
24:
Configurati
on
Pins
Table
25:
Boot
Pins
Table
26:
Startup-Times
74567899234589012344567890302
2222222333333444444444445566
19012345678901225683456677 11222222222233333345555555
Copyr
ig
ht
©
Siemens
AG
2014.
All
rights
rese
r
ved.
T
ech
n
ica
l
data
subject
to
change.
5
ERTE
C 2
00P
Data Sh
ee
t
Ve
rsion
1.
1
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