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JEDEC Standard No. 209-4D
Contents
1 Scope ......................................................................................................................................................1
2 Die configuration, Package ballout & Pin Definition ................................................................................2
2.1 Die configuration...............................................................................................................................2
2.2 Pad Order .........................................................................................................................................5
2.2.1 Pad Order for dual channel .............................................................................................................5
2.2.2 Pad Order for single channel ...............................................................................................6
2.3 Package Ballout................................................................................................................................7
2.3.1 272 ball 15 mm x 15 mm 0.4 mm pitch, Quad-Channel POP FBGA (top view) Using Variation
VFFCDB for MO-273.......................................................................................................7
2.3.2 LPDDR4 34x34 Quad x16 Channel (Fits 14x14 0.4 mm pitch) - Using MO-317A...............8
2.3.3 144 ball ePoP MCP One-Channel FBGA (top view) using MO-323A..................................9
2.3.4 200 Ball Packages .............................................................................................................10
2.3.4.1 200 Ball x32 Discrete Package, 0.80 mm x 0.65 mm using MO-311 .............................10
2.3.4.2 200 ball 1CHx16 Discrete Package, 0.80 mm x 0.65 mm using MO-311.......................11
2.3.5 203 ball Discrete Two-Channel FBGA (top view) using MO-311.......................................13
2.3.6 432 ball x64 HDI Discrete Package, 0.50mm x 0.50mm (MO-313)...................................14
2.3.7 324 ball x64 Non HDI Discrete Package ...........................................................................15
2.3.8 275 ball MCP Two-Channel FBGA (top view) using MO-276............................................16
2.3.9 254 ball e•MMC MCP Two-Channel FBGA (top view) using MO-276 ...............................17
2.3.10 254 ball UFS MCP Two-Channel FBGA (top view) using MO-276..................................18
2.3.11 254 ball e•MMC MCP One Channel FBGA (top view) using MO-276 .............................19
2.3.12 LPDDR4/4X Single Channel MCP (x8 NAND) Using MO-TBD .......................................20
2.3.13 LPDDR4/4X Single Channel MCP (eMMC) Using MO-TBD............................................21
2.3.14 LPDDR4/4X 254 ball NAND MCP Two-Channel FBGA (top view) using MO-276 ..........22
2.4 Package Ballout..............................................................................................................................23
2.5 ZQ Wiring........................................................................................................................................24
2.6 Pad Definition and Description .......................................................................................................25
2.6.1 Dual channel per die device ..............................................................................................25
2.6.2 Single channel per die device............................................................................................26
3 Functional Description ...........................................................................................................................27
3.1 LPDDR4 SDRAM Addressing.........................................................................................................28
3.2 Simplified LPDDR4 State Diagram.................................................................................................35
3.3 Power-up, Initialization and Power-off Procedure...........................................................................38
3.3.1 Voltage Ramp and Device Initialization .............................................................................38
3.3.2 Reset Initialization with Stable Power................................................................................41
3.3.3 Power-off Sequence ..........................................................................................................41
3.3.4 Uncontrolled Power-Off Sequence ....................................................................................41
3.4 Mode Register Definition ................................................................................................................42
3.4.1 Mode Register Assignment and Definition in LPDDR4 SDRAM........................................42
4 Command Definitions and Timing Diagrams .........................................................................................77
4.1 Activate Command .........................................................................................................................77
4.2 8-Bank Device Operation................................................................................................................78
