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**重要提醒: 解读已更新到v2, 最后更新时间2021-7-11 161631** ** 本文档不仅仅是LP4 spec标准文档,而是spec的注释解读 ** ** 翻译成中文? 当然不是翻译, 翻译放到网站上随便都可以翻译出来,此文是带着理解的解读! 深挖spec内部的原理,让您事半功倍!不要被spec卡住您的前途! ** 因为解读是注释,即文中黄色或绿色下划线的注解,试读看不到,正在想方法如何显示给大家看。 ** 行业标准: 作者有数年spec经验. ** 专业: 数年dram问题debug,spec解读专业到位。 ** 咨询: 承诺文档解读有疑问,可以免费每天3个问题的解答。 ** 退款: 作者承诺如果对于文档解读不满意,可线下联系作者申请退款. ** 更新: 不定期进行文档更新,保证每读一遍都有不一样的感受。 ** 再次提醒: 试读看到的是标准LP4 spec, 批注注释才是本文档的价值所在!! 千万不要以为仅仅是LP4 spec!!
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JEDEC
STANDARD
Low Power Double Date Rate 4
(LPDDR4)
JESD209-4B
(Revision of JESD209-4A, November 2015)
FEBRUARY 2017
JEDEC SOLID STATE TECHNOLOGY ASSOCIATION
NOTICE
JEDEC standards and publications contain material that has been prepared, reviewed, and
approved through the JEDEC Board of Directors level and subsequently reviewed and approved
by the JEDEC legal counsel.
JEDEC standards and publications are designed to serve the public interest through eliminating
misunderstandings between manufacturers and purchasers, facilitating interchangeability and
improvement of products, and assisting the purchaser in selecting and obtaining with minimum
delay the proper product for use by those other than JEDEC members, whether the standard is to
be used either domestically or internationally.
JEDEC standards and publications are adopted without regard to whether or not their adoption
may involve patents or articles, materials, or processes. By such action JEDEC does not assume
any liability to any patent owner, nor does it assume any obligation whatever to parties adopting
the JEDEC standards or publications.
The information included in JEDEC standards and publications represents a sound approach to
product specification and application, principally from the solid state device manufacturer
viewpoint. Within the JEDEC organization there are procedures whereby a JEDEC standard or
publication may be further processed and ultimately become an ANSI standard.
No claims to be in conformance with this standard may be made unless all requirements stated in
the standard are met.
Inquiries, comments, and suggestions relative to the content of this JEDEC standard or
publication should be addressed to JEDEC at the address below, or refer to www.jedec.org under
Standards and Documents for alternative contact information.
Published by
©JEDEC Solid State Technology Association 2017
3103 North 10th Street
Suite 240 South
Arlington, VA 22201-2107
This document may be downloaded free of charge; however JEDEC retains the
copyright on this material. By downloading this file the individual agrees not to
charge for or resell the resulting material.
PRICE: Contact JEDEC
Printed in the U.S.A.
All rights reserved
PLEASE!
DON’T VIOLATE
THE
LAW!
This document is copyrighted by JEDEC and may not be
reproduced without permission.
For information, contact:
JEDEC Solid State Technology Association
3103 North 10th Street
Suite 240 South
Arlington, VA 22201-2107
or refer to www.jedec.org under Standards-Documents/Copyright Information.
JEDEC Standard No. 209-4B
Page 1
LOW POWER DOUBLE DATA RATE (LPDDR) 4
From JEDEC Board Ballot JCB-16-51, formulated under the cognizance of the JC-42.6 Subcommittee on
Low Power Memories.)
1Scope
This document defines the LPDDR4 standard, including features, functionalities, AC and DC
characteristics, packages, and ball/signal assignments. The purpose of this specification is to define the
minimum set of requirements for a JEDEC compliant 16 bit per channel SDRAM device with either one or
two channels. LPDDR4 dual channel device density ranges from 4 Gb through 32 Gb and single channel
density ranges from 2 Gb through 16 Gb. This document was created using aspects of the following
standards: DDR2 (JESD79-2), DDR3 (JESD79-3), DDR4 (JESD79-4), LPDDR (JESD209), LPDDR2
(JESD209-2) and LPDDR3 (JESD209-3).
Each aspect of the standard was considered and approved by committee ballot(s). The accumulation of
these ballots was then incorporated to prepare the LPDDR4 standard.
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