JEDEC
STANDARD
Addendum No. 1 to JESD209-4 - Low
Power Double Data Rate 4X
(LPDDR4X)
JESD209-4-1
JANUARY 2017
JEDEC SOLID STATE TECHNOLOGY ASSOCIATION
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JEDEC Standard No. 209-4-1
-i-
Addendum No. 1 to JESD209-4 - LOW POWER DOUBLE DATA RATE 4X (LPDDR4X)
Contents
1 Scope ................................................................................................................................. 1
2 Package ballout and Pin Definition ................................................................................. 2
2.1 Pad Order ........................................................................................................................... 2
2.2 Single Channel Pad Order ................................................................................................. 3
2.3 LPDDR4X packages ........................................................................................................... 4
2.3.1 LPDDR4 34x34 Quad x16 Channel (Fits 14x14 0.4 mm pitch) – Using MO-317A ............. 4
2.3.2 144 ball ePoP MCP One-Channel FBGA (top view) using MO-323A ................................. 5
2.3.3 200-ball x32 Discrete Package, 0.80 mm x 0.65 mm using MO-311 .................................. 6
2.3.4 432-ball x64 HDI Discrete Package, 0.50 mm x 0.50 mm (MO-313) .................................. 7
2.3.5 254 ball e•MMC MCP Two-Channel FBGA (top view) using MO-276 .............................. 10
2.3.6 254 ball UFS MCP Two-Channel FBGA (top view) using MO-276 ................................... 11
2.3.7 254 ball e•MMC MCP One Channel FBGA (top view) using MO-276 .............................. 10
2.4 Pad Definition and Description ......................................................................................... 13
2.5 Mode Register Definition .................................................................................................. 14
3 Command Definitions and Timing Diagrams ............................................................... 23
3.1 Pull Up/Pull Down Driver Characteristics and Calibration ............................................... 23
3.2 ODT Mode Register and ODT Characteristics ................................................................ 23
3.3 On Die Termination for DQ, DQS and DMI ...................................................................... 25
3.4 Output Driver and Termination Register Temperature and Voltage Sensitivity ............... 27
4 AC and DC Operating Conditions ................................................................................. 28
4.1 Recommended DC Operating Conditions for low voltage ................................................ 28
4.2 Single Ended Output Slew Rate ....................................................................................... 28
4.3 Differential Output Slew Rate ........................................................................................... 29
5 V
REF
Specifications ......................................................................................................... 30
5.1 CA Internal V
REF
Specifications ......................................................................................... 30
5.2 DQ Internal V
REF
Specifications ........................................................................................ 30
6 Power-up, Initialization and Power-off Procedure ....................................................... 30
7 ODT Mode Register and ODT State Table .................................................................... 33
8 Core Timing ..................................................................................................................... 34
