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JESD209-4-1A LPDDR4X
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JESD209-4-1A LPDDR4X
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JEDEC
STANDARD
Addendum No. 1 to JESD209-4 - Low
Power Double Data Rate 4X
(LPDDR4X)
JESD209-4-1A
(Revision of JESD209-4-1, January 2017)
February 2021
JEDEC SOLID STATE TECHNOLOGY ASSOCIATION
NOTICE
JEDEC standards and publications contain material that has been prepared, reviewed, and
approved through the JEDEC Board of Directors level and subsequently reviewed and approved
by the JEDEC legal counsel.
JEDEC standards and publications are designed to serve the public interest through eliminating
misunderstandings between manufacturers and purchasers, facilitating interchangeability and
improvement of products, and assisting the purchaser in selecting and obtaining with minimum
delay the proper product for use by those other than JEDEC members, whether the standard is to
be used either domestically or internationally.
JEDEC standards and publications are adopted without regard to whether or not their adoption
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any liability to any patent owner, nor does it assume any obligation whatever to parties adopting
the JEDEC standards or publications.
The information included in JEDEC standards and publications represents a sound approach to
product specification and application, principally from the solid state device manufacturer
viewpoint. Within the JEDEC organization there are procedures whereby a JEDEC standard or
publication may be further processed and ultimately become an ANSI standard.
No claims to be in conformance with this standard may be made unless all requirements stated in
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Published by
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This document is copyrighted by JEDEC and may not be
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For information, contact:
JEDEC Solid State Technology Association
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Suite 240 South
Arlington, VA 22201-2107
or refer to www.jedec.org under Standards-Documents/Copyright Information.
JEDEC Standard No. 209-4-1A
-i-
Addendum No. 1 to JESD209-4 - LOW POWER DOUBLE DATA RATE 4X (LPDDR4X)
Contents
1
Scope ................................................................................................................................. 1
2 Package Ballout and Pin Definition ................................................................................ 2
Pad Order .......................................................................................................................... 2
2.2 Single Channel Pad Order ............................................................................................... 3
2.3 LPDDR4X packages.......................................................................................................... 4
2.3.1 LPDDR4 34x34 Quad x16 Channel (Fits 14x14 0.4 mm pitch) – Using MO-317A ........ 4
2.3.2 144 ball ePoP MCP One-Channel FBGA (top view) using MO-323A ............................ 5
2.3.3 200-ball x32 Discrete Package, 0.80 mm x 0.65 mm using MO-311 ............................. 6
2.3.4 432-ball x64 HDI Discrete Package, 0.50 mm x 0.50 mm (MO-313) .............................. 7
2.3.5 254 ball e•MMC MCP Two-Channel FBGA (top view) using MO-276 ............................ 8
2.3.6 254 ball UFS MCP Two-Channel FBGA (top view) using MO-276 ................................ 9
2.4 Pad Definition and Description ..................................................................................... 13
2.5 Mode Register Definition ............................................................................................... 14
3 Command Definitions and Timing Diagrams ............................................................... 25
3.1 Pull Up/Pull Down Driver Characteristics and Calibration ......................................... 25
3.2 ODT Mode Register and ODT Characteristics ............................................................. 25
3.2 ODT Mode Register and ODT Characteristics (cont’d) ............................................... 26
3.3 On Die Termination for DQ, DQS and DMI .................................................................... 27
3.4 Output Driver and Termination Register Temperature and Voltage Sensitivity ....... 29
3.5 Single-ended mode for Clock and Strobe .................................................................... 30
3.5.1 Combination of Mode Register setting and ODT termination .................................... 30
3.5.2 Restriction of Single-ended mode ................................................................................ 30
3.5.3 Switching sequence between Differential and Single-ended ..................................... 31
3.5.4 VRCG Enable timing ....................................................................................................... 36
3.5.5 Command bus training procedure ................................................................................ 38
3.5.6 Mode Register Function with two physical registers .................................................. 41
3.5.7 Reference level for Single-ended mode ....................................................................... 42
3.5.8 AC parameters for Single Ended (SE) .......................................................................... 43
4 AC and DC Operating Conditions ................................................................................. 44
4.1 Recommended DC Operating Conditions for low voltage .......................................... 44
4.2 Single Ended Output Slew Rate .................................................................................... 44
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