加法器设计（三）超前进位加法器（Verilog）
超前进位加法器
module add4_head ( a, b, ci, s, pp, gg);
input[3:0] a;
input[3:0] b;
input ci;
output[3:0]s;
output pp;
output gg;
wire[3:0] p;
wire[3:0] g;
wire[2:0] c;
assign p[0] = a[0] ^ b[0];
assign p[1] = a[1] ^ b[1];
assign p[2] = a[2] ^ b[2];
assign p[3] = a[3] ^ b[3];
assign g[0] = a[0] & b[0];
assign g[1] = a[1] & b[1];
assign g[2] = a[2] & b[2];
assign g[3] = a[3] & b[3];
assign c[0] = (p[0] & ci) | g[0];
assign c[1] = (p[1] & c[0]) | g[1];
assign c[2] = (p[2] & c[1]) | g[2];
assign pp = p[3] & p[2] & p[1] & p[0];
assign gg= g[3] | (p[3] & (g[2] | p[2] & (g[1] | p[1] & g[0])));
assign s[0] = p[0] ^ ci;
assign s[1] = p[1] ^ c[0];
assign s[2] = p[2] ^ c[1];
assign s[3] = p[3] ^ c[2];
endmodule
首先要明确几个概念：
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