//=============================================================================
// FILE: OS_MMU.C
// DESC:
// HIST:
//=============================================================================
#include "OS_ARCH.H"
#include "ARM920T.H"
// ----------------------------------------------------------------------------
// Translation Table(C2):
// 31 14 13 0
// +-----------------------------+-------------------------------+
// | Translation Table Base | 0 |
// +-----------------------------+-------------------------------+
//
// Level One Descriptor:
// 31 20 19 12 11 10 9 8 5 4 3 2 1 0
// +----------------------+-----------+-----+-+--------+-+-+-+-+-+
// | |0|0| Fault
// +----------------------------------------+-+--------+-+---+-+-+
// | Coarse page table base address | | Domain |1| |0|1| Coarse Page Table
// +----------------------+-----------+-----+-+--------+-+-+-+-+-+
// | Section base address | | AP |0| Domain |1|C|B|1|0| Section
// +----------------------+-----------+-----+-+--------+-+-+-+-+-+
// | Fine page table base address | | Domain |1| |1|1| Fine Page Table
// +----------------------------------+-------+--------+-+---+-+-+
//
// Level Two Descriptor:
// 31 16 15 12 11 10 9 8 7 6 5 4 3 2 1 0
// +--------------------------+--------+-----+---+---+---+-+-+-+-+
// | |0|0| Fault
// +--------------------------+--------+-----+---+---+---+-+-+-+-+
// | Large page base address | | ap3 |ap2|ap1|ap0|C|B|0|1| Large Page
// +--------------------------+--------+-----+---+---+---+-+-+-+-+
// | Small page base address | ap3 |ap2|ap1|ap0|C|B|1|0| Small Page
// +-----------------------------------+-----+---+---+---+-+-+-+-+
// | Tiny page base address | | ap|C|B|1|1| Tiny Page
// +-----------------------------------------+-------+---+-+-+-+-+
//
// ----------------------------------------------------------------------------
#define DESC_FAULT_PAGE 0x00 // 0b00, Fault page
#define DESC_CPAGE_FLAG 0x11 // 0b10001, Coarse page
#define DESC_SECTION_FLAG 0x12 // 0b10010, Section
#define DESC_FPAGE_FLAG 0x13 // 0b10011, Fine page
#define DESC_LPAGE_FLAG 0x01 // 0b0001, Large page
#define DESC_SPAGE_FLAG 0x02 // 0b0010, Small page
#define DESC_TPAGE_FLAG 0x03 // 0b0011, Tiny page
#define DOMAIN_NR15 (0xF<<5)
#define DOMAIN_NR14 (0xE<<5)
#define DOMAIN_NR13 (0xD<<5)
#define DOMAIN_NR12 (0xC<<5)
#define DOMAIN_NR11 (0xB<<5)
#define DOMAIN_NR10 (0xA<<5)
#define DOMAIN_NR9 (0x9<<5)
#define DOMAIN_NR8 (0x8<<5)
#define DOMAIN_NR7 (0x7<<5)
#define DOMAIN_NR6 (0x6<<5)
#define DOMAIN_NR5 (0x5<<5)
#define DOMAIN_NR4 (0x4<<5)
#define DOMAIN_NR3 (0x3<<5)
#define DOMAIN_NR2 (0x2<<5)
#define DOMAIN_NR1 (0x1<<5)
#define DOMAIN_NR0 (0x0<<5)
// ----------------------------------------------------------------------------
// [8:5]=Domain, specify one of the 16 possible domains
// (held in the domain access control register)
//
// Domain access control register format:
// 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
// +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+-+-+-+-+-+-+-+-+-+-+
// | | | | | | | | | | | | | | | | |
// +-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+---+---+---+---+---+
// 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
// ----------------------------------------------------------------------------
#define DOMAIN15_BITS(m) ((m)<<30)
#define DOMAIN14_BITS(m) ((m)<<28)
#define DOMAIN13_BITS(m) ((m)<<26)
#define DOMAIN12_BITS(m) ((m)<<24)
#define DOMAIN11_BITS(m) ((m)<<22)
#define DOMAIN10_BITS(m) ((m)<<20)
#define DOMAIN9_BITS(m) ((m)<<18)
#define DOMAIN8_BITS(m) ((m)<<16)
#define DOMAIN7_BITS(m) ((m)<<14)
#define DOMAIN6_BITS(m) ((m)<<12)
#define DOMAIN5_BITS(m) ((m)<<10)
#define DOMAIN4_BITS(m) ((m)<<8)
#define DOMAIN3_BITS(m) ((m)<<6)
#define DOMAIN2_BITS(m) ((m)<<4)
#define DOMAIN1_BITS(m) ((m)<<2)
#define DOMAIN0_BITS(m) ((m)<<0)
// ----------------------------------------------------------------------------
// Interpreting access control bits in domain access control register:
//
// Value Meaning Description
// ------+---------+-------------------------------------------------------------
// 00 No access Any access generates a domain fault
// 01 Client Accesses are checked against the access permission bits in the section or page descriptor
// 10 Reserved Reserved. Currently behaves like the no access mode
// 11 Manager Accesses are not checked against the access permission bits so a permission fault cannot be generated
// ----------------------------------------------------------------------------
#define DOMAIN_NOACCESS 0x0
#define DOMAIN_CLIENT 0x1
#define DOMAIN_RESERVED 0x2
#define DOMAIN_MANAGER 0x3
// ----------------------------------------------------------------------------
// Interpreting access permission (AP) bits:
// Supervisor User
// AP S(C1) R(C1) permissions permissions Description
// -----+-----+-----+-----------+-----------+----------------------------------
// 00 0 0 No access No access Any access generates a permission fault
// 00 1 0 Read only No access Only Supervisor read permitted
// 00 0 1 Read only Read only Any write generates a permission fault
// 00 1 1 Reserved - -
// 01 x x Read/write No access Access allowed only in Supervisor mode
// 10 x x Read/write Read only Writes in User mode cause permission fault
// 11 x x Read/write Read/write All access types permitted in both modes
// xx 1 1 Reserved - -
// ----------------------------------------------------------------------------
#define AP_sNA_uNA (0x0<<10)
#define AP_sRW_uNA (0x1<<10)
#define AP_sRW_uRO (0x2<<10)
#define AP_sRW_uRW (0x3<<10)
// ----------------------------------------------------------------------------
// DCache and write buffer configuration:
//
// CB Description
// ----+------------------------------
// 00 Noncached, nonbuffered (NCNB)
// 01 Noncached, buffered (NCB)
// 10 Cached write-through mode (WT)
// 11 Cached write-back mode (WB)
// ----------------------------------------------------------------------------
#define CB_NCNB (0x0<<2)
#define CB_NCB (0x1<<2)
#define CB_WT (0x2<<2)
#define CB_WB (0x3<<2)
// ----------------------------------------------------------------------------
// Only use the section table, the size of each section is 1MB.
//
// Board: S3C2440
// Exception vector start address: 0x30000000
// SFR, physical address: 0x48000000-0x5FFFFFFF
// 64MB SDARAM, physical address: 0x30000000-0x33FFFFFF
//
// Bank7: 0x3400_0000 - 0x3FFF_FFFF (SDARM, Not exist)
// Bank6: 0x3000_0000 - 0x33FF_FFFF (SDARM, 64MB)
// Bank5: 0x2800_0000 - 0x2FFF_FFFF ( ROM,128MB)
// Bank4: 0x2000_0000 - 0x27FF_FFFF ( ROM,128MB)
// Bank3: 0x1800_0000 - 0x1FFF_FFFF ( ROM,128MB)
// Bank2: 0x1000_0000 - 0x17FF_FFFF ( ROM,128MB)
// Bank1: 0x0800_0000 - 0x0FFF_FFFF ( ROM
