CLK0_DIVIDE_BY=1
CLK0_DUTY_CYCLE=50
CLK0_MULTIPLY_BY=5
CLK0_PHASE_SHIFT=0
COMPENSATE_CLOCK=CLK0
GATE_LOCK_SIGNAL=NO
INCLK0_INPUT_FREQUENCY=50000
INTENDED_DEVICE_FAMILY="Cyclone II"
INVALID_LOCK_MULTIPLIER=5
LPM_TYPE=altpll
OPERATION_MODE=NORMAL
PORT_ACTIVECLOCK=PORT_UNUSED
PORT_ARESET=PORT_USED
PORT_CLKBAD0=PORT_UNUSED
PORT_CLKBAD1=PORT_UNUSED
PORT_CLKLOSS=PORT_UNUSED
PORT_CLKSWITCH=PORT_UNUSED
PORT_CONFIGUPDATE=PORT_UNUSED
PORT_FBIN=PORT_UNUSED
PORT_INCLK0=PORT_USED
PORT_INCLK1=PORT_UNUSED
PORT_LOCKED=PORT_USED
PORT_PFDENA=PORT_UNUSED
PORT_PHASECOUNTERSELECT=PORT_UNUSED
PORT_PHASEDONE=PORT_UNUSED
PORT_PHASESTEP=PORT_UNUSED
PORT_PHASEUPDOWN=PORT_UNUSED
PORT_PLLENA=PORT_UNUSED
PORT_SCANACLR=PORT_UNUSED
PORT_SCANCLK=PORT_UNUSED
PORT_SCANCLKENA=PORT_UNUSED
PORT_SCANDATA=PORT_UNUSED
PORT_SCANDATAOUT=PORT_UNUSED
PORT_SCANDONE=PORT_UNUSED
PORT_SCANREAD=PORT_UNUSED
PORT_SCANWRITE=PORT_UNUSED
PORT_clk0=PORT_USED
PORT_clk1=PORT_UNUSED
PORT_clk2=PORT_UNUSED
PORT_clk3=PORT_UNUSED
PORT_clk4=PORT_UNUSED
PORT_clk5=PORT_UNUSED
PORT_clkena0=PORT_UNUSED
PORT_clkena1=PORT_UNUSED
PORT_clkena2=PORT_UNUSED
PORT_clkena3=PORT_UNUSED
PORT_clkena4=PORT_UNUSED
PORT_clkena5=PORT_UNUSED
PORT_extclk0=PORT_UNUSED
PORT_extclk1=PORT_UNUSED
PORT_extclk2=PORT_UNUSED
PORT_extclk3=PORT_UNUSED
VALID_LOCK_MULTIPLIER=1
DEVICE_FAMILY="Cyclone II"
CBX_AUTO_BLACKBOX=ALL
areset
inclk
inclk
clk
locked
pwm.rar （88个子文件） 
pwm 
pwm.pin 20KB pwm.fit.summary 585B pwm.v.bak 186B db pwm.eco.cdb 161B prev_cmp_pwm.qmsg 48KB pwm.db_info 137B pwm.sld_design_entry.sci 154B logic_util_heursitic.dat 0B pwm.eda.rpt 6KB simulation modelsim pwm_modelsim.xrf 1KB pwm_run_msim_rtl_verilog.do.bak4 528B modelsim.ini 11KB pwm_run_msim_rtl_verilog.do.bak10 528B pwm_run_msim_rtl_verilog.do.bak3 528B pwm_run_msim_rtl_verilog.do.bak 528B pwm_run_msim_rtl_verilog.do.bak5 528B rtl_work _vmake 26B pwm_vlg_tst verilog.prw 2KB _primary.dat 459B _primary.vhd 82B verilog.psm 5KB _primary.dbs 788B pll verilog.prw 10KB _primary.dat 3KB _primary.vhd 254B verilog.psm 28KB _primary.dbs 3KB _temp pwm verilog.prw 1KB _primary.dat 261B _primary.vhd 254B verilog.psm 3KB _primary.dbs 570B _info 747B pwm.vt.bak 3KB pll.qip 0B pwm_run_msim_rtl_verilog.do.bak9 528B pwm_run_msim_rtl_verilog.do.bak8 528B pwm_v.sdo 3KB pwm_run_msim_rtl_verilog.do.bak11 528B pwm_run_msim_rtl_verilog.do 528B greybox_tmp 
cbx_args.txt 1KB pwm_run_msim_rtl_verilog.do.bak2 528B pwm_run_msim_rtl_verilog.do.bak1 528B msim_transcript 4KB pwm_run_msim_rtl_verilog.do.bak6 528B pwm.vt 3KB vsim.wlf 64KB pwm_run_msim_rtl_verilog.do.bak7 528B pwm.vo 10KB pwm.sft 108B pwm.qws 527B pll.ppf 470B pll.qip 436B pwm.pof 512KB pwm.dpf 239B pwm.fit.smsg 513B incremental_db compiled_partitions pwm.root_partition.cmp.dfp 33B pwm.root_partition.map.cdb 1KB pwm.db_info 153B pwm.root_partition.map.dpi 3KB pwm.root_partition.cmp.cdb 2KB pwm.root_partition.cmp.kpt 208B pwm.root_partition.hbdb.cdb 879B pwm.root_partition.cmp.hdb 10KB pwm.root_partition.map.hdb 10KB pwm.root_partition.map.kpt 213B pwm.root_partition.cmp.re.rcfdb 974B pwm.root_partition.cmp.logdb 4B pwm.root_partition.cmp.rcfdb 959B README 653B pwm_nativelink_simulation.rpt 1007B pwm.fit.rpt 79KB pwm.v 187B pwm.map.summary 449B greybox_tmp cbx_args.txt 1KB pwm.bsf 2KB pwm.done 26B pwm.sof 148KB pwm.qsf 4KB pll_inst.v 116B pwm.tan.summary 749B pwm.tan.rpt 13KB pll_bb.v 11KB pwm.map.rpt 58KB pwm.qpf 1KB pwm.asm.rpt 7KB pwm.flow.rpt 8KB pll.v 15KB
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