你看这个东西对你有用么?
我怎么就没感觉时序同步 就非得要个 PLL 呢?
不倍频用 PLL 干什么啊 !
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter is
GENERIC
(
mode : std_logic_vector(3 downto 0) := "1111"
);
port(clk : in std_logic;
updown : in std_logic;
clkout : out std_logic);
end counter;
architecture Behavioral of counter is
signal cnt : std_logic_vector(3 downto 0);
signal flag : std_logic; --每一个 clkout 时针周期只做一次调整.
begin
process(clk, cnt)
begin
if clk'event and clk = '1' then
if cnt = '0' & mode(2 downto 0) then
clkout <= '1';
elsif cnt = mode then
clkout <= '0';
flag <= '0';
end if;
if updown = '1' and cnt = "0100" and flag = '0' then
cnt <= cnt;
flag <= '1';
elsif updown = '0' and cnt = "1010" and flag = '0' then
cnt <= cnt + 2;
flag <= '1';
else
cnt <= cnt +1;
end if;
评论12