LS1043ADPAARM.pdf

QorIQ LS1043A Data Path Acceleration Architecture (DPAA) Reference Manual Supports LS1023A LS1043A

介绍QorIQ平台数据路径加速架构(DPAA) ，深入了解QMAN、BMAN、FMAN和外设加速器-FTF演讲资料.pdf

DPAA 深入了解QMAN、BMAN、FMAN和外设加速器

P5020 QorIQ Integrated Multicore Communication Processor Family Reference Manual

PowerPC 5020 data sheet

Freescale官方 QorIQ处理器T1024RDB 原理图（ORCAD+pdf）.rar

The QorIQ® dual-core T1024 and T1023 and single-core T1014 and T1013 communications processors combine 64-bit cores, built on Power Architecture® technology, with high-performance Data Path Acceleration Architecture (DPAA) and network peripheral bus interfaces required networking, telecommunications and industrial networked applications. The QorIQ T Series platform offers optimized features for the industrial market, including a display interface unit for HMI, the QUICC Engine® for industrial protocol offload and ECC support for high reliability “always on” applications. SCH-28624_revC.rar (407.42 KB, 下载次数: 13 ) T1024RDB revC DSN (PDF).pdf (1.09 MB, 下载次数: 16 )

QorIQ SDK v2.0-1703 Documentation QORIQ-SDK-2.0-IC-REV0.pdf

QorIQ SDK v2.0-1703 PowerPC P1010 2020 等开发必备文档！

LS1043ASECRM.pdf

QorIQ LS1043A Security (SEC) Reference Manual Document Number: LS1043ASECRM Rev. 1, 07/2017

P4080_Reference_Manual,_Rev_G.pdf

This reference manual defines the functionality of the P4080 QorIQ Integrated Host Controller. This device integrates eight PowerPC™ processor cores based on Power Architecture™ technology, two frame manager units, other datapath acceleration blocks, with system logic required for networking, telecommunications, and wireless infrastructure applications. The e500mc processor core is a low-power implementation of the family of reduced instruction set computing (RISC) embedded processors that implement the Book E definition of the Power Architecture

LS1043ARM.pdf

QorIQ LS1043A Reference Manual

LS1021A.pdf

NXP的LS1021A芯片资料

P2020 _Design_Checklist.pdf

This document provides recommendations for new designs based on the P2020 QorIQ integrated processor. This chip combines dual e500v2 processor cores built on Power Architecture® technology with system logic required for networking, wireless infrastructure, and telecommunications applications

Freescale官方 QorIQ处理器T4240RDB 原理图（ORCAD+pdf）.rar

包含： 参考设计板T4240RDB电路图.pdf T4240PB.pdf T4240RDBQS.pdf T4240RDB.rar 带有24个虚拟内核的T4240是QorIQ T系列的旗舰产品。该产品与T4160 (16个虚拟内核)及T4080 (8个虚拟内核)共同构成了T4系列。该系列可通过引脚兼容的封装提供高达3倍的性能可伸缩性。 这些产品的运行频率最高可达1.8 GHz，集成1Gbps和10Gpbs以太网、硬件加速以及先进的系统外设，适用于希望通过一个SoC整合控制和数据平台处理的应用，例如服务卡、微型服务器、ADC、WOC、智能NICS和RNC等 T4240PB[1].pdf 487.91 KB, 下载次数: 122 , 下载积分: 资产 -2 信元, 下载支出 2 信元 T4240 Product Brief T4240RDBSCH[1].pdf 2.49 MB, 下载次数: 178 , 下载积分: 资产 -2 信元, 下载支出 2 信元 原理图 T4240RDBQS[1].pdf 2.27 MB, 下载次数: 136 , 下载积分: 资产 -2 信元, 下载支出 2 信元 Quick Start Guide T4240RDB.rar 1.63 MB, 下载次数: 238 , 下载积分: 资产 -2 信元, 下载支出 2 信元 orcad原理图 收藏收藏 分享分享 支持支持2

P2020RM.pdf

QorIQ P2平台系列包含P2020与P2010通信处理器，可实现单线程极高性能功耗比，适用于联网、电信、军事以及工业领域中的各种应用。在45nm技术低功耗平台上，该系列产品最高可实现1.2 GHz双核以及单核频率。 QorIQ P2系列集成了一套丰富的接口，其中包括SerDes、千兆以太网、PCI-Express、RapidIO®技术以及USB。三个10/100/1000以太网端口支持先进的数据包分析、流量控制以及服务质量等特性以及IEEE® 1588时间标志。四个SerDes巷道可在两个串行RapidIO端口、三个PCI Express端口以及两个SGMII端口之间进行分配。

QorIQ-SDK-1.4-IC-RevA.pdf

The Freescale SDK documentation is written for software developers and system engineers with a technical background.The Linux operating system supports many architectures including Power™, and many aspects of its use are common to all of them. As a general statement, the reader is assumed to have a working knowledge of Linux.

P1022RM.pdf

Altera’s new Cyclone® IV FPGA device family extends the Cyclone FPGA series leadership in providing the market’s lowest-cost, lowest-power FPGAs, now with a transceiver variant. Cyclone IV devices are targeted to high-volume, cost-sensitive applications, enabling system designers to meet increasing bandwidth requirements while lowering costs. Built on an optimized low-power process, the Cyclone IV device family offers the following two variants: This document provides an overview of features and functionality of the QorIQ chip communications processor. The chip combines dual Power Architecture e500v2 processor cores with system logic required for media, communications, and industrial applications. The chip offers an excellent combination of protocol and interface support including dual high-performance CPU cores, a DDR2/DDR3 memory controller, two enhanced threespeed Ethernet controllers with SGMII, RMII, and RGMII support, a secure digital interface, two USB 2.0 interfaces, audio/visual interfaces, and three PCI Express controllers. The device also supports the IEEE 1588TM precision time protocol for network synchronization over Ethernet. This manual is written from the perspective of the chip; the information also applies to the P1013, with the exception that the P1013 is a single-core device. This section describes the features of the device.

QORIQ-SDK-2.0-IC-REV0.pdf

QORIQ-SDK-2.0-IC-REV0 。。。。。。。。。。。。。。。。。。。。。。。。。。。。。

APF-SNT-T1361.pdf

Troubleshooting Techniques for QorIQ eTSEC and DPAA Platforms

Freescale官方 QorIQ处理器T1040RDB 原理图（ORCAD+pdf）.rar

概述 QorIQ T1040四核和T1020双核通信处理器可支持两个或4个集成式64位e5500 Power Architecture®处理器内核，提供网络和通信所需的高性能数据通路加速架构(DPAA)和网络外设接口。 T1040和T1020是业界首款集成了千兆以太网交换机的64位嵌入式处理器。T系列适用于混合控制和数据平台应用，如固定路由器、交换机、嵌入式接入设备、防火墙和其他数据包过滤应用，以及通用嵌入式计算。它具备较高的集成度，可提供卓越的性能优势，简化硬件和软件设计。 T1系列器件是业界最具可扩展性和引脚兼容性的通信处理器之一 – 为向更高性能的QorIQ T2081器件迁移提供了一条引脚兼容的途径。 T1040RDB_0116_Reversion_B.rar (492.93 KB, 下载次数: 137 ) T1040RDB_SCH0116.pdf (461.69 KB, 下载次数: 134 ) 处理器 , 防火墙 , 可扩展性 , 路由器 , 软件设计

RAD5545 SpaceVPX_SBC.pdf

SPACEVPX单板计算机资料。 The SBC is designed to support operation as either a payload or system controller in a SpaceVPX backplane. Based on BAE Systems’ RAD5545 or RAD5515 QorIQ® Power Architecture® radiation-hardened SoC processor, the SBC offers both high performance and high I/O throughput. It includes 4 GBytes of DDR3 SDRAM with error correction at 800 MTransfers/ second and 1 GBytes of triple modular redundant non-volatile flash memory and optional 4MB MRAM. Up to four RapidIO ports at 10 Gbits/second each and 12 SpaceWire links at 320 Mbits/second each are provided to the SpaceVPX backplane. An optional daughter card with PCI, RapidIO, and/ or SpaceWire interfaces can be used to personalize the SBC for unique needs.