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P2020

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标题《P2020处理器参考手册》和描述《P2020 QorIQ Integrated Processor Reference Manual》指出了本文档是关于Freescale公司生产的P2020集成处理器的技术参考资料。P2020是QorIQ产品线的一部分，针对嵌入式处理器市场设计，用于高性能网络和通信应用。QorIQ系列处理器基于e500v2核心，专注于提供高速数据处理能力和丰富功能。文档标签“P2020 文档”表明该文档是专门为P2020处理器准备的，它是开发人员、工程师和技术人员获取P2020处理器技术信息的权威来源。从提供的部分内容中，我们可以提炼出以下关键知识点： 1. 概述：文档开始于对P2020处理器的综合介绍，包括其基本功能和特性，为读者提供处理器设计和应用背景。内容涉及处理器的主要架构、性能参数以及芯片级别的关键特点。 2. 应用示例：文档中提到了P2020处理器的应用场景，例如LTE和WiMax基带应用以及线路卡控制平面应用。这些信息有助于设计者了解P2020处理器如何适用于特定的网络和通信领域。 3. 架构概览：此处详细描述了P2020处理器的内部架构，包括核心模块、内存单元、e500核心一致性模块(ECM)以及地址映射。此外，还介绍了集成的安全引擎(SEC)、增强的以太网控制器、USB 2.0、高速I/O接口等特性，强调了P2020处理器在数据传输和处理方面的多功能性。 4. 高速I/O接口：包括PCI Express接口、Serial RapidIO接口、SGMII接口和高速接口复用技术。这些接口是现代网络设备和通信系统的关键组件，支持高速数据交换和设备互联。 5. 程序化中断控制器(PIC)：中断控制器管理各种事件的优先级和处理流程，是操作系统中响应各种硬件和软件事件的重要组件。 6. 直接内存访问(DMA)、I2C、DUART以及增强型本地总线控制器(eLBC)：这些是处理器内部集成的接口和控制器，用于与外设交互，支持DMA操作来减轻CPU负担，I2C用于低速外设的串行通信，DUART用于双通道的串行通信，而eLBC支持扩展的本地总线。 7. 设备启动位置和启动序列器：这些特性决定了设备如何从不同位置启动，以及它们的启动顺序。这对于固件开发和引导加载程序编写至关重要。 8. 内存映射：这部分描述了P2020处理器的内存映射架构，包括配置、控制和状态寄存器(CCSR)。CCSR内存映射是处理器内部各种控制和状态信息的存储区域，外部处理器和本地处理器都能访问CCSR内存空间。 9. 局部访问窗口(LAW)：LAW提供了处理器内部模块与内存之间的高效访问方式。LAW的配置对于优化内存访问和设备性能具有重要作用。 10. 电源管理：为了优化能耗效率，文档中涉及了P2020处理器的电源管理技术。它允许设备在不同的功耗状态之间转换，以适应不同的性能需求和电源限制。 11. 系统性能监控：性能监控功能对于开发者和维护人员了解系统运行状况非常重要，通过监控可以分析、诊断和优化处理器和系统的性能。根据手册的结构，读者可以按章节顺序深入理解P2020处理器的每个功能模块以及如何与整个系统配合工作。内容详细到各个寄存器级别的配置，是处理器设计、固件开发和应用编程的重要参考资料。

P2020 QorIQ Integrated Processor

Reference Manual

Supports: P2020 and P2010

Document Number: P2020RM

Rev. 2, 12/2012

Contents

Section number Title Page

Chapter 1

Overview

1.1 Overview.......................................................................................................................................................................67

1.1.1 Block diagram............................................................................................................................................67

1.1.2 Critical performance parameters................................................................................................................68

1.1.3 Chip-level features.....................................................................................................................................69

1.2 Application examples....................................................................................................................................................70

1.2.1 LTE and WiMax baseband application......................................................................................................70

1.2.2 Line card control plane application............................................................................................................71

1.3 Architecture overview...................................................................................................................................................72

1.3.1 e500v2 cores and memory unit..................................................................................................................72

1.3.2 e500 coherency module (ECM) and address map.....................................................................................73

1.3.3 Integrated security engine (SEC)...............................................................................................................74

1.3.4 Enhanced three-speed Ethernet controllers................................................................................................74

1.3.5 Universal serial bus (USB) 2.0..................................................................................................................76

1.3.6 Enhanced secure digital host controller.....................................................................................................76

1.3.7 Enhanced serial peripheral interface (eSPI)...............................................................................................77

1.3.8 DDR SDRAM controller...........................................................................................................................77

1.3.9 High speed I/O interfaces...........................................................................................................................78

1.3.9.1 PCI Express interfaces...........................................................................................................78

1.3.9.2 Serial RapidIO interfaces.......................................................................................................79

1.3.9.3 SGMII....................................................................................................................................79

1.3.9.4 High-speed interface multiplexing.........................................................................................79

1.3.10 Programmable interrupt controller (PIC)...................................................................................................80

1.3.11 DMA, I2C, DUART, and eLBC................................................................................................................80

1.3.12 Device boot locations.................................................................................................................................81

1.3.13 Boot sequencer...........................................................................................................................................82

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Section number Title Page

1.3.14 Power management....................................................................................................................................82

1.3.15 System performance monitor.....................................................................................................................82

Chapter 2

Memory Map

2.1 Overview.......................................................................................................................................................................83

2.2 Configuration, control, and status registers..................................................................................................................84

2.2.1 Accessing CCSR memory from the local processor..................................................................................85

2.2.2 Accessing CCSR memory from external masters......................................................................................85

2.2.3 Organization of CCSR space.....................................................................................................................86

2.2.3.1 General utilities registers.......................................................................................................86

2.2.3.1.1 General utilities register organization.............................................................87

2.2.3.2 Programmable interrupt controller registers..........................................................................88

2.2.3.3 Serial RapidIO registers.........................................................................................................89

2.2.3.4 Device-specific utilities registers...........................................................................................90

2.2.4 CCSR address map.....................................................................................................................................91

2.3 Local access windows...................................................................................................................................................94

2.3.1 Precedence of local access windows..........................................................................................................95

2.3.2 Configuring local access windows.............................................................................................................95

2.3.3 Distinguishing local access windows from other mapping functions........................................................95

2.3.4 Illegal interaction between local access windows and DDR chip selects..................................................96

2.3.5 Local address map example.......................................................................................................................96

2.4 Local access window registers......................................................................................................................................97

2.4.1 Local access window 0 base address register (LAW_LAWBARn)..........................................................99

2.4.2 Local access window 0 attribute register (LAW_LAWARn)....................................................................99

2.5 Address translation and mapping units.........................................................................................................................101

2.5.1 Address translation ....................................................................................................................................101

2.5.2 Outbound ATMUs.....................................................................................................................................102

2.5.3 Inbound ATMUs........................................................................................................................................103

2.5.3.1 Illegal interaction between inbound ATMUs and LAWs......................................................103

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Section number Title Page

Chapter 3

Signal Descriptions

3.1 Signals overview...........................................................................................................................................................105

3.2 Configuration signals sampled at reset.........................................................................................................................116

3.3 Output signal states during reset...................................................................................................................................118

Chapter 4

Reset, Clocking, and Initialization

4.1 Overview.......................................................................................................................................................................119

4.2 External signal descriptions..........................................................................................................................................119

4.2.1 System control signals...............................................................................................................................120

4.2.2 Clock signals..............................................................................................................................................121

4.3 Accessing configuration, control, and status registers..................................................................................................122

4.3.1 Updating CCSRBAR.................................................................................................................................122

4.3.2 Accessing alternate configuration space....................................................................................................123

4.3.3 Boot page translation.................................................................................................................................124

4.3.4 Boot sequencer...........................................................................................................................................124

4.4 Reset Memory Map/Register Definition.......................................................................................................................124

4.4.1 Configuration, control, and status registers base address register (Reset_CCSRBAR)............................125

4.4.2 Alternate configuration base address register (Reset_ALTCBAR)...........................................................126

4.4.3 Alternate configuration attribute register (Reset_ALTCAR)....................................................................126

4.4.4 Boot page translation register (Reset_BPTR)............................................................................................127

4.5 Functional description...................................................................................................................................................127

4.5.1 Reset operations.........................................................................................................................................127

4.5.1.1 Soft reset................................................................................................................................128

4.5.1.2 Hard reset...............................................................................................................................128

4.5.2 Power-on reset sequence............................................................................................................................128

4.5.3 Power-on reset configuration.....................................................................................................................130

4.5.3.1 System PLL ratio...................................................................................................................131

4.5.3.2 DDR PLL Ratio.....................................................................................................................132

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