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QorIQ™ P2020

Integrated Processor

Reference Manual

Supports

P2020

P2010

P2020RM

Rev. 0

07/2009

Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc.

The Power Architecture and Power.org word marks and the Power and Power.org logos

and related marks are trademarks and service marks licensed by Power.org. The

described product contains a PowerPC processor core. The PowerPC name is a

trademark of IBM Corp. and used under license. RapidIO is a registered trademark of

the RapidIO Trade Association. IEEE 802.3, 802.3u, 802.3x, 802.3z, 802.3ac, and

802.11i are registered trademarks of the Institute of Electrical and Electronics

Engineers, Inc. (IEEE). This product is not endorsed or approved by the IEEE. All other

product or service names are the property of their respective owners.

Information in this document is provided solely to enable system and software

implementers to use Freescale Semiconductor products. There are no express or

implied copyright licenses granted hereunder to design or fabricate any integrated

circuits or integrated circuits based on the information in this document.

Freescale Semiconductor reserves the right to make changes without further notice to

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Document Number: P2020RM

Rev. 0, 07/2009

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QorIQ P2020 Integrated Processor Reference Manual, Rev. 0

Freescale Semiconductor iii

Contents

Paragraph

Number Title

Page

Number

Co nt ents

About This Book

Audience ...........................................................................................................................cxi

Organization......................................................................................................................cxi

Suggested Reading..........................................................................................................cxiv

General Information....................................................................................................cxiv

Related Documentation...............................................................................................cxiv

Conventions .....................................................................................................................cxv

Signal Conventions.........................................................................................................cxvi

Acronyms and Abbreviations ........................................................................................cxvii

Part I

Overview

Chapter 1

Overview

1.1 P2020 Overview .............................................................................................................. 1-2

1.1.1 Block Diagram............................................................................................................. 1-2

1.1.2 Critical Performance Parameters ................................................................................. 1-2

1.1.3 Chip-Level Features..................................................................................................... 1-3

1.2 P2020 Application Examples........................................................................................... 1-4

1.2.1 LTE and WiMax Baseband Application ...................................................................... 1-4

1.2.2 Line Card Control Plane Application .......................................................................... 1-5

1.3 P2020 Architecture Overview ......................................................................................... 1-6

1.3.1 e500v2 Cores and Memory Unit.................................................................................. 1-6

1.3.2 e500 Coherency Module (ECM) and Address Map .................................................... 1-7

1.3.3 Integrated Security Engine (SEC)................................................................................ 1-7

1.3.4 Enhanced Three-Speed Ethernet Controllers............................................................... 1-8

1.3.5 Universal Serial Bus (USB) 2.0................................................................................... 1-9

1.3.6 Enhanced Secure Digital Host Controller.................................................................... 1-9

1.3.7 Serial Peripheral Interface (SPI)................................................................................ 1-10

1.3.8 DDR SDRAM Controller .......................................................................................... 1-10

1.3.9 High Speed I/O Interfaces.......................................................................................... 1-11

1.3.9.1 PCI Express Interfaces........................................................................................... 1-11

1.3.9.2 Serial RapidIO Interfaces ...................................................................................... 1-11

1.3.9.3 SGMII....................................................................................................................1-12

QorIQ P2020 Integrated Processor Reference Manual, Rev. 0

iv Freescale Semiconductor

Contents

Paragraph

Number Title

Page

Number

1.3.9.4 High-Speed Interface Multiplexing....................................................................... 1-12

1.3.10 Programmable Interrupt Controller (PIC).................................................................. 1-12

1.3.11 DMA, I

C, DUART, and Enhanced Local Bus Controller........................................ 1-13

1.3.12 Device Boot Locations............................................................................................... 1-13

1.3.13 Boot Sequencer.......................................................................................................... 1-14

1.3.14 Power Management ................................................................................................... 1-14

1.3.15 System Performance Monitor.................................................................................... 1-14

Chapter 2

Memory Map

2.1 Overview.......................................................................................................................... 2-1

2.2 Local Access Windows.................................................................................................... 2-1

2.2.1 Local Access Window Registers ................................................................................. 2-2

2.2.1.1 Local Access Window n Base Address Registers

(LAWBAR0–LAWBAR11)................................................................................. 2-3

2.2.1.2 Local Access Window n Attributes Registers

(LAWAR0–LAWAR11)....................................................................................... 2-4

2.2.2 Configuring Local Access Windows ........................................................................... 2-5

2.2.3 Distinguishing Local Access Windows from Other Mapping Functions .................... 2-5

2.2.4 Illegal Interaction Between Local Access Windows and DDR

Chip Selects ............................................................................................................. 2-6

2.2.5 Local Address Map Example....................................................................................... 2-6

2.3 Address Translation and Mapping Units ......................................................................... 2-7

2.3.1 Address Translation ..................................................................................................... 2-8

2.3.2 Outbound ATMUs........................................................................................................ 2-8

2.3.3 Inbound ATMUs .......................................................................................................... 2-8

2.3.3.1 Illegal Interaction Between Inbound ATMUs and LAWs ....................................... 2-9

2.4 Configuration, Control, and Status Registers .................................................................. 2-9

2.4.1 Accessing CCSR Memory from External Masters.................................................... 2-10

2.4.2 Organization of CCSR Space .................................................................................... 2-10

2.4.2.1 General Utilities Registers..................................................................................... 2-11

2.4.2.1.1 General Utilities Register Organization............................................................. 2-11

2.4.2.2 Programmable Interrupt Controller Registers ....................................................... 2-12

2.4.2.3 Serial RapidIO Registers ....................................................................................... 2-14

2.4.2.4 Device-Specific Utilities Registers........................................................................ 2-14

2.4.3 CCSR Address Map................................................................................................... 2-15

QorIQ P2020 Integrated Processor Reference Manual, Rev. 0

Freescale Semiconductor v

Contents

Paragraph

Number Title

Page

Number

Chapter 3

Signal Descriptions

3.1 Signals Overview.............................................................................................................3-1

3.2 Configuration Signals Sampled at Reset ....................................................................... 3-20

3.3 Output Signal States During Reset ................................................................................ 3-22

Chapter 4

Reset, Clocking, and Initialization

4.1 Overview.......................................................................................................................... 4-1

4.2 External Signal Descriptions ........................................................................................... 4-1

4.2.1 System Control Signals................................................................................................ 4-2

4.2.2 Clock Signals............................................................................................................... 4-3

4.3 Memory Map/Register Definition ................................................................................... 4-4

4.3.1 Local Configuration Control........................................................................................ 4-4

4.3.1.1 Accessing Configuration, Control, and Status Registers......................................... 4-5

4.3.1.1.1 Updating CCSRBAR........................................................................................... 4-5

4.3.1.1.2 Configuration, Control, and Status Base Address Register (CCSRBAR)........... 4-6

4.3.1.2 Accessing Alternate Configuration Space............................................................... 4-6

4.3.1.2.1 Alternate Configuration Base Address Register (ALTCBAR)............................ 4-7

4.3.1.2.2 Alternate Configuration Attribute Register (ALTCAR)...................................... 4-7

4.3.1.3 Boot Page Translation.............................................................................................. 4-8

4.3.1.3.1 Boot Page Translation Register (BPTR).............................................................. 4-8

4.3.2 Boot Sequencer............................................................................................................ 4-9

4.4 Functional Description..................................................................................................... 4-9

4.4.1 Reset Operations.......................................................................................................... 4-9

4.4.1.1 Soft Reset................................................................................................................. 4-9

4.4.1.2 Hard Reset ...............................................................................................................4-9

4.4.2 Power-On Reset Sequence......................................................................................... 4-10

4.4.3 Power-On Reset Configuration.................................................................................. 4-11

4.4.3.1 System PLL Ratio.................................................................................................. 4-12

4.4.3.2 DDR PLL Ratio ..................................................................................................... 4-12

4.4.3.3 e500 Core PLL Ratios ........................................................................................... 4-13

4.4.3.4 Boot ROM Location .............................................................................................. 4-14

4.4.3.5 Host/Agent Configuration ..................................................................................... 4-15

4.4.3.6 I/O Port Selection .................................................................................................. 4-16

4.4.3.7 CPU Boot Configuration ....................................................................................... 4-18

4.4.3.8 Boot Sequencer Configuration .............................................................................. 4-19

4.4.3.9 DDR SDRAM Type............................................................................................... 4-19

4.4.3.10 SerDes Reference Clock Configuration................................................................. 4-19

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