Addendum List for Revision 8
MPC5604B Reference Manual Errata, Rev. 1
Freescale Semiconductor 3
Chapter 22, FlexCAN,
throughout chapter
Remove references throughout the chapter to “low-cost MCUs.”
Chapter 22, FlexCAN, page
429
Added this Note in the RTR field description of Table 22-4 (Message Buffer Structure field
description):
Note: Do not configure the last Message Buffer to be the RTR frame.
Chapter 22, FlexCAN, page
461
In Section 22.4.9.4, Protocol timing, updated the Note following Figure 22-16 (CAN engine
clocking scheme) to read: “This clock selection feature may not be available in all MCUs. A
particular MCU may not have a PLL, in which case it would have only the oscillator clock, or
it may use only the PLL clock feeding the FlexCAN module. In these cases, the CLK_SRC bit
in the CTRL Register has no effect on the module operation.”
Chapter 22, FlexCAN, page
462
Updated the table title of Table 22-20 from “CAN Standard Compliant Bit Time Segment
Settings” to “Bosch CAN 2.0B standard compliant bit time segment settings.”
Chapter 22, FlexCAN, page
463
In Section 22.4.9.4, Protocol timing, updated the Note following Table 22-20 to read: “Other
combinations of Time Segment 1 and Time Segment 2 can be valid. It is the user’s
responsibility to ensure the bit time settings are in compliance with the CAN standard. For bit
time calculations, use an IPT (Information Processing Time) of 2, which is the value
implemented in the FlexCAN module.”
Chapter 25, Analog-to-Digital
Converter (ADC), page
In Section 28.3.5.2, Presampling channel enable signals, in Table 28-7, Presampling voltage
selection based on PREVALx fields, in the 01 row, change the “Presampling voltage” field to:
V1 = V
DD_HV_ADC0
or V
DD_HV_ADC1
.
Chapter 25, Analog-to-Digital
Converter (ADC), page 597
In Section 25.3.2, Analog clock generator and conversion timings, remove the paragraph:
The direct clock should basically be used only in low power mode when the device is using
only the 16 MHz fast internal RC oscillator, but the conversion still requires a 16 MHz clock
(an 8 MHz clock is not fast enough). In all other cases, the ADC should use the clock divided
by two internally.
Chapter 25, Analog-to-Digital
Converter (ADC), p. 600
In Section 25.3.4.2, CTU in trigger mode, replace the sentence:
If another CTU conversion is triggered before the end of the conversion, that request is
discarded.
with:
If another CTU conversion is triggered before the end of the conversion, that request is
discarded. However, if the CTU has triggered a conversion that is still ongoing on a channel,
it will buffer a second request for the channel and wait for the end of the first conversion before
requesting another conversion. Thus, two conversion requests close together will both be
serviced.
Chapter 25, Analog-to-Digital
Converter (ADC), page 603
Add Note to Section 25.3.10, Auto-clock-off mode:
Note: The auto-clock-off feature cannot operate when the digital interface runs at the same
rate as the analog interface. This means that when MCR.ADCCLKSEL = 1, the analog clock
will not shut down in IDLE mode.
Table 1. MPC5604BCRM Rev 8 Addenda
Location Description
doublewei12014-08-17我认为和需要消耗的积分有点不符，不是很有用。
chyb20022015-09-29恩，英文原版的，硬着头皮看吧
