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Freescale Confidential Proprietary

Preliminary—Subject to Change Without Notice

P4080 QorIQ

Integrated Multicore

Communication Processor

Family Reference Manual

Supports

P4080

P4040

P4080RM

Rev. G

04/2010

Freescale, the Freescale logo, CodeWarrior, ColdFire are trademarks of

Freescale Semiconductor, Inc. Reg. U.S. Pat. & Tm. Off. CoreNet and QorIQ

are trademarks of Freescale Semiconductor, Inc.

Portions of Chapter 16, “Universal Serial Bus Interface,” relating to the EHCI

specification is provided “As Is” with no warranties whatsoever, including

any warranty of merchantability, non-infringement, fitness for any particular

purpose, or any warranty otherwise arising out of any proposal, specification

or sample. Intel disclaims all liability, including liability for infringement of any

proprietary rights, relating to use of information in the EHCI specification.

Intel may make changes to the EHCI specifications at any time, without

notice.

All other product or service names are the property of their respective

owners. The Power Architecture and Power.org word marks and the Power

and Power.org logos and related marks are trademarks and service marks

licensed by Power.org. RapidIO is a registered trademark of the RapidIO

Trade Association. IEEE 802.3, 802.1, and 1588 are registered trademarks

of the Institute of Electrical and Electronics Engineers, Inc. (IEEE). This

product is not endorsed or approved by the IEEE.

Freescale Confidential Proprietary

Preliminary—Subject to Change Without Notice

Information in this document is provided solely to enable system and software

implementers to use Freescale Semiconductor products. There are no express or

implied copyright licenses granted hereunder to design or fabricate any integrated

circuits or integrated circuits based on the information in this document.

Freescale Semiconductor reserves the right to make changes without further notice to

any products herein. Freescale Semiconductor makes no warranty, representation or

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Semiconductor was negligent regarding the design or manufacture of the part.

Document Number: P4080RM

Rev. G, 04/2010

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P4080 QorIQ Integrated Multicore Communication Processor Family Reference Manual, Rev. G

Freescale Semiconductor Freescale Confidential Proprietary iii

Preliminary—Subject to Change Without Notice

Contents

Paragraph

Number Title

Page

Number

Co nt ents

About This Book

General Information.....................................................................................................ccxvii

Related Documentation...............................................................................................ccxviii

Part I

SoC Architecture Overview

Chapter 1

Overview

1.1 Introduction...................................................................................................................... 1-1

1.2 QorIQ P4080 Features ..................................................................................................... 1-1

1.3 Block Diagram................................................................................................................. 1-3

1.4 Application Examples...................................................................................................... 1-3

1.4.1 Multicore Processing Scenarios................................................................................... 1-4

1.4.2 QorIQ P4080 Applications .......................................................................................... 1-5

1.4.2.1 Virtual Private Network (VPN)/ IP Services Router............................................... 1-5

1.4.2.2 Security Services Blade for Switch or Server.......................................................... 1-6

1.4.2.3 Wireless Infrastructure/Radio Node Controller....................................................... 1-6

1.4.2.4 High-Performance Compute Blade.......................................................................... 1-7

1.5 Subsystem Features.......................................................................................................... 1-8

1.5.1 e500 Core and Cache Memory Complex..................................................................... 1-8

1.5.2 CoreNet Fabric and Address Map ............................................................................. 1-10

1.5.3 Memory Complex...................................................................................................... 1-10

1.5.3.1 DDR Memory Controllers ..................................................................................... 1-10

1.5.3.2 PreBoot Loader and Nonvolatile Memory Interfaces............................................ 1-11

1.5.3.2.1 Enhanced Local Bus Controller......................................................................... 1-11

1.5.3.2.2 Serial Memory Controllers ................................................................................ 1-11

1.5.4 Universal Serial Bus (USB) 2.0................................................................................. 1-12

1.5.5 High-Speed Peripheral Interface Complex................................................................ 1-12

1.5.5.1 PCI Express Controllers ........................................................................................ 1-12

1.5.5.2 Serial RapidIO ....................................................................................................... 1-13

1.5.6 Datapath Acceleration Architecture (DPAA) ............................................................ 1-13

1.5.6.1 Datapath Acceleration Architecture Programming Model.................................... 1-14

1.5.6.2 Definitions ............................................................................................................. 1-15

1.5.7 Major DPAA Components......................................................................................... 1-16

1.5.7.1 Frame Manager...................................................................................................... 1-17

1.5.7.1.1 Network Interfaces ............................................................................................ 1-17

1.5.7.1.2 Parse Function ................................................................................................... 1-17

1.5.7.1.3 Distribution and Policing................................................................................... 1-18

P4080 QorIQ Integrated Multicore Communication Processor Family Reference Manual, Rev. G

iv Freescale Confidential Proprietary Freescale Semiconductor

Preliminary—Subject to Change Without Notice

Contents

Paragraph

Number Title

Page

Number

1.5.7.2 Queue Manager...................................................................................................... 1-19

1.5.7.3 Buffer Manager...................................................................................................... 1-19

1.5.7.4 Security Engine (SEC 4.0)..................................................................................... 1-20

1.5.7.5 Pattern Matching Engine (PME) 2.0 ..................................................................... 1-21

1.6 Resource Partitioning and QorIQ Trust Architecture .................................................... 1-22

1.6.1 e500mc MMU and Embedded Hypervisor................................................................ 1-22

1.6.2 Peripheral Access Management Unit (PAMU).......................................................... 1-23

1.6.3 Secure Boot and Sensitive Data Protection ............................................................... 1-23

1.7 Advanced Power Management ...................................................................................... 1-24

1.8 Debug Support ............................................................................................................... 1-25

Chapter 2

Memory Map

2.1 Overview.......................................................................................................................... 2-1

2.2 Global Source and Target IDs.......................................................................................... 2-2

2.3 Local Access Windows.................................................................................................... 2-4

2.3.1 Local Access Window Registers ................................................................................. 2-5

2.3.1.1 Local Access Window n Base Address Register High (LAWBARH0–LAWBARH31)

2-9

2.3.1.2 Local Access Window n Base Address Register Low (LAWBARL0–LAWBARL31)

2-10

2.3.1.3 Local Access Window n Attributes Registers (LAWAR0–LAWAR31)................ 2-11

2.3.2 Precedence of Local Access Windows ...................................................................... 2-12

2.3.3 Configuring Local Access Windows ......................................................................... 2-12

2.3.4 Distinguishing Local Access Windows from Other Mapping Functions .................. 2-13

2.3.5 SRAM Windows........................................................................................................ 2-13

2.3.6 Local Address Map Example..................................................................................... 2-14

2.4 Address Translation and Mapping Units ....................................................................... 2-15

2.4.1 Address Translation ................................................................................................... 2-15

2.4.2 Outbound ATMUs...................................................................................................... 2-16

2.4.3 Inbound ATMUs ........................................................................................................ 2-16

2.4.3.1 Illegal Interaction Between Inbound ATMUs and LAWs ..................................... 2-16

2.5 Configuration, Control, and Status Register Map.......................................................... 2-16

2.5.1 Accessing CCSR Memory from the Local Processor................................................ 2-17

2.5.2 Accessing CCSR Memory from External Masters.................................................... 2-17

2.5.3 Accessing Reserved Registers and Bits..................................................................... 2-17

2.5.4 Organization of CCSR Memory ................................................................................ 2-18

2.5.5 General Module Register Layout............................................................................... 2-18

2.5.6 Interrupt Controller and CCSR.................................................................................. 2-19

2.5.7 Serial RapidIO and CCSR ......................................................................................... 2-20

P4080 QorIQ Integrated Multicore Communication Processor Family Reference Manual, Rev. G

Freescale Semiconductor Freescale Confidential Proprietary v

Preliminary—Subject to Change Without Notice

Contents

Paragraph

Number Title

Page

Number

2.5.8 CCSR Address Map................................................................................................... 2-20

Chapter 3

Signal Descriptions

3.1 Signals Overview.............................................................................................................3-1

3.2 Dedicated Configuration Signals ................................................................................... 3-13

3.2.1 I/O Voltage Select ...................................................................................................... 3-13

3.3 Configuration Signals Sampled at Reset ....................................................................... 3-14

3.4 Signal Multiplexing Details........................................................................................... 3-14

3.4.1 IEEE 1588 and GPIO Signal Multiplexing................................................................ 3-15

3.4.2 Frame Manager 1 dTSEC1 and USB1 Signal Multiplexing...................................... 3-16

3.4.3 Frame Manager 2 dTSEC1, Frame Manager 1 dTSEC2, and USB2 Signal Multiplexing

3-17

3.4.4 UART and GPIO Signal Multiplexing....................................................................... 3-18

3.4.5 I2C3, eSDHC, and GPIO Signal Multiplexing.......................................................... 3-19

3.4.6 I2C4 and Debug Signal Multiplexing........................................................................ 3-19

3.4.7 MPIC and GPIO Signal Multiplexing ....................................................................... 3-20

3.4.8 MPIC and Debug Signal Multiplexing...................................................................... 3-20

3.4.9 eSPI and eSDHC Signal Multiplexing....................................................................... 3-20

3.4.10 DMA1, Debug, and GPIO Signal Multiplexing........................................................ 3-20

3.4.11 DMA2, Debug, and GPIO Signal Multiplexing........................................................ 3-21

3.4.12 SerDes Lane Assignments and Multiplexing............................................................. 3-22

3.5 SerDes Control Memory Map/Register Definition........................................................ 3-24

3.5.1 SerDes Reset Control Register (SRDSBnRSTCTL) .................................................3-27

3.5.2 SerDes PLL Control Register 0 (SRDSBnPLLCR0) ................................................ 3-28

3.5.3 SerDes PLL Control Register 1 (SRDSBnPLLCR1) ................................................ 3-29

3.5.4 SerDes Transmit Calibration Control Register (SRDSTCALCR)............................. 3-30

3.5.5 SerDes Receive Calibration Control Register (SRDSRCALCR).............................. 3-30

3.5.6 SerDes General Register 0 (SRDSGR0).................................................................... 3-31

3.5.7 SerDes Protocol Converter Configuration Register 0 (SRDSPCCR0)...................... 3-32

3.5.8 SerDes Protocol Converter Configuration Register 1 (SRDSPCCR1)...................... 3-33

3.5.9 SerDes Protocol Converter Configuration Register 2 (SRDSPCCR2)...................... 3-35

3.5.10 Bank 1 General Control Register 0 (B1GCRA0–B1GCRJ0).................................... 3-37

3.5.11 Bank 1 General Control Register 1 (B1GCRA1–B1GCRJ1).................................... 3-39

3.5.12 Bank 1 Transmit Equalization Control Register 0 (B1TECRA0–B1TECRJ0).......... 3-41

3.5.13 Bank 1 Transition Tracking Loop Control Register 0 (B1TTLCRA0–B1TTLCRJ0) 3-42

3.5.14 Bank 2 General Control Register 0 (B2GCRA0–B2GCRD0)...................................3-44

3.5.15 Bank 2 General Control Register 1 (B2GCRA1–B2GCRD1)...................................3-46

3.5.16 Bank 2 Transmit Equalization Control Register 0 (B2TECRA0–B2TECRD0)........ 3-48

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