Section number Title Page
1.3.12.4 High-speed interface multiplexing.........................................................................................93
1.3.13 Programmable interrupt controller (PIC)...................................................................................................94
1.3.14 DMA, I2C, DUART, and eLBC................................................................................................................95
1.3.15 Device boot locations.................................................................................................................................96
1.3.16 Boot sequencer...........................................................................................................................................96
1.3.17 Power management....................................................................................................................................96
1.3.18 System performance monitor.....................................................................................................................96
Chapter 2
Memory Map
2.1 Introduction...................................................................................................................................................................99
2.2 Configuration, control, and status registers..................................................................................................................100
2.2.1 Accessing CCSR memory from the local processor..................................................................................101
2.2.2 Accessing CCSR memory from external masters......................................................................................101
2.2.3 Organization of CCSR space.....................................................................................................................102
2.2.3.1 General utilities registers.......................................................................................................102
2.2.3.1.1 General utilities register organization.............................................................103
2.2.3.2 Programmable interrupt controller registers..........................................................................104
2.2.3.3 Device-specific utilities registers...........................................................................................105
2.2.4 CCSR address map.....................................................................................................................................106
2.3 Memory_Map Memory Map/Register Definition........................................................................................................109
2.3.1 Local access window n base address register (Memory_Map_LAWBARn)............................................111
2.3.2 Local access window n attribute register (Memory_Map_LAWARn)......................................................111
2.4 Local access windows...................................................................................................................................................112
2.4.1 Precedence of local access windows..........................................................................................................113
2.4.2 Configuring local access windows.............................................................................................................113
2.4.3 Distinguishing local access windows from other mapping functions........................................................114
2.4.4 Illegal interaction between local access windows and DDR chip selects..................................................114
2.4.5 Local address map example.......................................................................................................................114
P1022 QorIQ Integrated Processor Reference Manual, Rev. 2, 04/2013
4 Freescale Semiconductor, Inc.
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