Vol. 33, No. 3 Journal of Semiconductors March 2012
A novel high speed lateral IGBT with a self-driven second gate
Hu Hao(胡浩)
and Chen Xingbi(陈星弼)
State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology
of China, Chengdu 610054, China
Abstract: A novel lateral IGBT with a second gate on the emitter portion is presented. A PMOS transistor, driven
by the proposed device itself, is used to short the PN junction at the emitter while turned off. Low on state voltage
and fast turn off speed are obtained without side-effects such as snapback I –V characteristics and difficulties of
process complexity. Numerical simulation results show a drop of fall time from 120 to 12 ns and no increase of on
state voltage.
Key words: lateral IGBT; second gate; high speed
DOI: 10.1088/1674-4926/33/3/034004 PACC: 7340L; 7340Q
1. Introduction
Insulated gate bipolar transistors (IGBTs) are widely used
because of the combination of MOS controlled switching capa-
bility and low on state voltage
Œ1; 2
. However, IGBTs produce a
current tailing effect during turn off due to the injection of mi-
nority carriers of the forward-biased PN junction at the emitter
and a long turn off time. Therefore, large turn off losses occur
as a result
Œ3
. Many methods are used to reduce turn off time
but all these require costs such as increase of on state voltage,
additional control terminal and external driving circuits
Œ46
. A
low voltage transistor is integrated in a vertical IGBT to short
the forward-biased PN junction during turn off to eliminate the
tail current and the transistor is turned off during on state to
ensure sufficient conductivity modulation in Ref. [7]. Driv-
ing circuits for the shorting transistor are also integrated into
the same chip. Through this way low on state voltage and fast
switching capability are combined together with neither an ad-
ditional control terminal nor external driving circuits. Such an
idea could be used in a lateral IGBT (LIGBT) for high voltage
power ICs (HVICs) and some necessary changes of the struc-
ture are needed. In Ref. [8] an additional passive gate is used
in a LIGBT and a field oxide PMOS transistor (PMOST) is
turned on during turn off to eliminate the injection of minority
carriers. There are some problems with the LIGBT in Ref. [8]
such as an additional pad or wiring over voltage sustaining re-
gion being needed, as said in Ref. [9]. Some improvements are
made in Ref. [9] but additional area is needed due to the lat-
eral diffusion of the n-well and the introduction of a floating
n-region.
In this paper, a LIGBT with a self-driven second gate is
presented to solve the problem of tailing current during turn
off without any difficulty of process complexity. A shorting
PMOST connected parallel to the PN junction at the emitter
turns on and off driven by a voltage taken from the drift re-
gion. That means neither additional control terminal nor exter-
nal driving circuits are needed. Its source–gate voltage varies
from near zero voltage during on state to a certain value during
turn off. This paper also presents numerical simulation results
by MEDICI
Œ10
.
2. Structure and operation of the proposed
LIGBT
Figure 1 illustrates the schematic cross-section of the pro-
posed LIGBT and its equivalent circuit. A p-layer and an n-well
satisfy the optimum variational lateral doping (VLD) condi-
tion
Œ11
. The VLD LIGBT is believed to be capable of sustain-
ing larger voltage in a shorter drift region length and conduct-
ing a higher current density
Œ12
. High n-well doping decreases
the on state voltage more and works as a buffer layer to prevent
the depletion region to get to the emitter.
A shorting PMOST, the gate of which is connected to the
end of the p-layer in the drift region, connects the emitter and
the floating electrode. The PMOST is turned off during on state
to ensure sufficient conductivity modulation. It is turned on
during turn off to short the forward-biased PN junction at the
emitter and translate electron current to emitter without minor-
ity carrier injection such as an LDMOS. The doping dose of the
p-layer in region A can be varied to get different gate voltages
of the shorting PMOST.
When the LIGBT is off, the p-layer is gradually depleted
and holes in the p-layer flow to the collector as the emitter volt-
age goes up. The p-layer in region A will be depleted com-
pletely at some value of the emitter voltage and a barrier is
built up between the holes in the p-island right to region A and
the p-layer left to it. The holes in the p-island will stop flowing
to the emitter due to the resistance of the barrier and the volt-
age between the p-island and the n-well below it stops grow-
ing. This means the source–gate voltage V
SG2
of the shorting
PMOST is fixed at a certain value. The p-layer left to region
A continues to deplete to sustain the emitter voltage. Because
a fixed source–gate voltage V
SG2
can be obtained, the short-
ing PMOST can use the same thin gate oxide as used in the
CMOS control circuits, instead of the field oxide used in Refs.
[8, 9]. The benefit of using a thin gate oxide is that the threshold
voltage can be lowered down to obtain a better on-state char-
Corresponding author. Email: huhao21@uestc.edu.cn
Received 15 August 2011, revised manuscript received 17 November 2011
c
2012 Chinese Institute of Electronics
034004-1
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