PCI Express
®
Base Specification
Revision 2.0
December 20, 2006
2
Revision Revision History DATE
1.0 Initial release. 07/22/02
1.0a Incorporated Errata C1-C66 and E1-E4.17. 04/15/03
1.1 Incorporated approved Errata and ECNs. 03/28/05
2.0 Added 5.0 GT/s data rate and incorporated approved Errata
and ECNs.
12/20/06
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®
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Copyright © 2002-2006 PCI-SIG
PCI EXPRESS BASE SPECIFICATION, REV. 2.0
3
Contents
OBJECTIVE OF THE SPECIFICATION.................................................................................... 21
DOCUMENT ORGANIZATION ................................................................................................ 21
DOCUMENTATION CONVENTIONS...................................................................................... 22
TERMS AND ACRONYMS........................................................................................................ 23
REFERENCE DOCUMENTS...................................................................................................... 29
1. INTRODUCTION ................................................................................................................ 31
1.1. A THIRD GENERATION I/O INTERCONNECT ................................................................... 31
1.2. PCI EXPRESS LINK......................................................................................................... 33
1.3. PCI EXPRESS FABRIC TOPOLOGY .................................................................................. 35
1.3.1. Root Complex........................................................................................................ 35
1.3.2. Endpoints .............................................................................................................. 36
1.3.3. Switch.................................................................................................................... 39
1.3.4. Root Complex Event Collector.............................................................................. 40
1.3.5. PCI Express to PCI/PCI-X Bridge........................................................................ 40
1.4. PCI EXPRESS FABRIC TOPOLOGY CONFIGURATION....................................................... 40
1.5. PCI EXPRESS LAYERING OVERVIEW.............................................................................. 41
1.5.1. Transaction Layer................................................................................................. 42
1.5.2. Data Link Layer.................................................................................................... 42
1.5.3. Physical Layer ...................................................................................................... 43
1.5.4. Layer Functions and Services............................................................................... 43
2. TRANSACTION LAYER SPECIFICATION ..................................................................... 47
2.1. T
RANSACTION LAYER OVERVIEW.................................................................................. 47
2.1.1. Address Spaces, Transaction Types, and Usage................................................... 48
2.1.2. Packet Format Overview ...................................................................................... 50
2.2. TRANSACTION LAYER PROTOCOL - PACKET DEFINITION............................................... 51
2.2.1. Common Packet Header Fields ............................................................................ 51
2.2.2. TLPs with Data Payloads - Rules......................................................................... 54
2.2.3. TLP Digest Rules .................................................................................................. 56
2.2.4. Routing and Addressing Rules.............................................................................. 56
2.2.5. First/Last DW Byte Enables Rules........................................................................ 59
2.2.6. Transaction Descriptor......................................................................................... 61
2.2.7. Memory, I/O, and Configuration Request Rules................................................... 66
2.2.8. Message Request Rules......................................................................................... 69
2.2.9. Completion Rules.................................................................................................. 80
2.3. H
ANDLING OF RECEIVED TLPS...................................................................................... 82
2.3.1. Request Handling Rules........................................................................................ 85
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2.3.2. Completion Handling Rules.................................................................................. 98
2.4. TRANSACTION ORDERING............................................................................................ 100
2.4.1. Transaction Ordering Rules ............................................................................... 100
2.4.2. Update Ordering and Granularity Observed by a Read Transaction................ 104
2.4.3. Update Ordering and Granularity Provided by a Write Transaction................ 105
2.5. VIRTUAL CHANNEL (VC) MECHANISM........................................................................ 105
2.5.1. Virtual Channel Identification (VC ID).............................................................. 108
2.5.2. TC to VC Mapping.............................................................................................. 109
2.5.3. VC and TC Rules................................................................................................. 110
2.6. ORDERING AND RECEIVE BUFFER FLOW CONTROL ..................................................... 111
2.6.1. Flow Control Rules............................................................................................. 112
2.7. DATA INTEGRITY ......................................................................................................... 122
2.7.1. ECRC Rules ........................................................................................................ 123
2.7.2. Error Forwarding............................................................................................... 127
2.8. COMPLETION TIMEOUT MECHANISM ........................................................................... 129
2.9. LINK STATUS DEPENDENCIES ...................................................................................... 130
2.9.1. Transaction Layer Behavior in DL_Down Status............................................... 130
2.9.2. Transaction Layer Behavior in DL_Up Status ................................................... 131
3. DATA LINK LAYER SPECIFICATION.......................................................................... 133
3.1. DATA LINK LAYER OVERVIEW .................................................................................... 133
3.2. DATA LINK CONTROL AND MANAGEMENT STATE MACHINE ...................................... 135
3.2.1. Data Link Control and Management State Machine Rules ................................ 136
3.3. FLOW CONTROL INITIALIZATION PROTOCOL ............................................................... 138
3.3.1. Flow Control Initialization State Machine Rules ............................................... 138
3.4. DATA LINK LAYER PACKETS (DLLPS)........................................................................ 142
3.4.1. Data Link Layer Packet Rules ............................................................................ 142
3.5. DATA INTEGRITY ......................................................................................................... 147
3.5.1. Introduction......................................................................................................... 147
3.5.2. LCRC, Sequence Number, and Retry Management (TLP Transmitter).............. 147
3.5.3. LCRC and Sequence Number (TLP Receiver).................................................... 159
4. PHYSICAL LAYER SPECIFICATION............................................................................ 167
4.1. INTRODUCTION ............................................................................................................ 167
4.2. L
OGICAL SUB-BLOCK................................................................................................... 167
4.2.1. Symbol Encoding ................................................................................................ 168
4.2.2. Framing and Application of Symbols to Lanes................................................... 171
4.2.3. Data Scrambling................................................................................................. 174
4.2.4. Link Initialization and Training.......................................................................... 176
4.2.5. Link Training and Status State Machine (LTSSM) Descriptions........................ 188
4.2.6. Link Training and Status State Rules.................................................................. 192
4.2.7. Clock Tolerance Compensation.......................................................................... 237
4.2.8. Compliance Pattern ............................................................................................ 239
4.2.9. Modified Compliance Pattern............................................................................. 240
4.3. E
LECTRICAL SUB-BLOCK ............................................................................................. 241
4.3.1. Maintaining Backwards Compatibility............................................................... 241
4.3.2. Jitter Budgeting and Measurement..................................................................... 243
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4.3.3. Transmitter Specification.................................................................................... 244
4.3.4. Receiver Specification......................................................................................... 259
4.3.5. Transmitter and Receiver DC Specifications...................................................... 273
4.3.6. Channel Specifications........................................................................................ 278
4.3.7. Reference Clock Specifications........................................................................... 285
5. POWER MANAGEMENT................................................................................................. 293
5.1. OVERVIEW ................................................................................................................... 293
5.1.1. Statement of Requirements.................................................................................. 294
5.2. L
INK STATE POWER MANAGEMENT............................................................................. 294
5.3. PCI-PM
SOFTWARE COMPATIBLE MECHANISMS......................................................... 299
5.3.1. Device Power Management States (D-States) of a Function.............................. 299
5.3.2. PM Software Control of the Link Power Management State.............................. 303
5.3.3. Power Management Event Mechanisms............................................................. 308
5.4. N
ATIVE PCI EXPRESS POWER MANAGEMENT MECHANISMS....................................... 315
5.4.1. Active State Power Management (ASPM) .......................................................... 315
5.5. A
UXILIARY POWER SUPPORT....................................................................................... 331
5.5.1. Auxiliary Power Enabling................................................................................... 331
5.6. POWER MANAGEMENT SYSTEM MESSAGES AND DLLPS............................................. 332
6. SYSTEM ARCHITECTURE ............................................................................................. 335
6.1. INTERRUPT AND PME SUPPORT ................................................................................... 335
6.1.1. Rationale for PCI Express Interrupt Model........................................................ 335
6.1.2. PCI Compatible INTx Emulation........................................................................ 336
6.1.3. INTx Emulation Software Model ........................................................................ 336
6.1.4. Message Signaled Interrupt (MSI/MSI-X) Support............................................. 336
6.1.5. PME Support....................................................................................................... 338
6.1.6. Native PME Software Model .............................................................................. 338
6.1.7. Legacy PME Software Model ............................................................................. 339
6.1.8. Operating System Power Management Notification........................................... 339
6.1.9. PME Routing Between PCI Express and PCI Hierarchies ................................ 339
6.2. E
RROR SIGNALING AND LOGGING................................................................................ 340
6.2.1. Scope................................................................................................................... 340
6.2.2. Error Classification............................................................................................ 340
6.2.3. Error Signaling................................................................................................... 342
6.2.4. Error Logging..................................................................................................... 349
6.2.5. Sequence of Device Error Signaling and Logging Operations .......................... 352
6.2.6. Error Message Controls ..................................................................................... 354
6.2.7. Error Listing and Rules ...................................................................................... 355
6.2.8. Virtual PCI Bridge Error Handling.................................................................... 359
6.3. VIRTUAL CHANNEL SUPPORT ...................................................................................... 360
6.3.1. Introduction and Scope....................................................................................... 360
6.3.2. TC/VC Mapping and Example Usage................................................................. 361
6.3.3. VC Arbitration .................................................................................................... 363
6.3.4. Isochronous Support........................................................................................... 371
6.4. DEVICE SYNCHRONIZATION......................................................................................... 374
6.5. L
OCKED TRANSACTIONS.............................................................................................. 375
