Installing the RocketIO Design Kit for HyperLynx
Copyright 2004 Mentor Graphics Corporation.
You can use the RocketIO(TM) Design Kit for HyperLynx(R) with
HyperLynx 7.5 GHz to perform pre-layout and post-layout signal
integrity analysis on designs using Xilinx(R) RocketIO SPICE models.
Revision history
================
Release v3.7a
1. New FFS files added that replicate the TLN files.
2. Updated documentation for FFS files.
Release v3.7
1. TLN files changed to accomodate package model changes made in Xilinx SIS Kit v3.7
- Removed flipchip.inc package model due to accuracy concerns and added more
s-parameter package models and a w-element package model.
2. Removed .pls fit files for old package information.
3. Removed eye mask file (bsw.mask) and updated documentation with instructions for
eye mask creation by user.
Before you begin installation
=============================
This document contains installation instructions for the Xilinx
Virtex-II Pro Signal Integrity Simulation Kit and for the RocketIO
Design Kit for HyperLynx. For installation and licensing instructions
for Eldo, HSPICE(R), and HyperLynx, see the documentation supplied
with those products.
To analyze the designs supplied in the RocketIO Design Kit for
HyperLynx, the following items must be installed on the computer:
- Mentor Graphics Eldo or Synopsys(R) HSPICE SPICE simulator.
- HyperLynx v7.5. If you need to download updated HyperLynx
software, visit http://www.mentor.com/supportnet.
Requirement: The SPICE simulator and HyperLynx v7.5 must be
installed on the same computer.
- HyperLynx LineSim GHz license.
- Xilinx Virtex-II Pro Signal Integrity Simulation Kit v3.7 or newer.
The kit contains encrypted Eldo files, encrypted HSPICE files, and
a User Guide.
For information about downloading the kit, see the Downloading Xilinx
and HyperLynx kits section below.
- RocketIO Design Kit for HyperLynx. The kit contains an installation
program to install LineSim schematic files and to configure LineSim
to use the Xilinx Virtex-II Pro Signal Integrity Simulation Kit
files.
Requirement: Install the RocketIO Design Kit for HyperLynx --AFTER--
installing HyperLynx 7.5 and the Xilinx Virtex-II Pro Signal
Integrity Simulation Kit.
For information about downloading the kit, see the Downloading Xilinx
and HyperLynx kits section below.
Downloading Xilinx and HyperLynx kits
=====================================
Perform the following steps:
1. Visit http://www.xilinx.com/support/software/spice/protected/spice-download.htm.
Requirement: You must have a Xilinx account to visit the above Web
page. To obtain a Xilinx account, visit
http://www.xilinx.com/support/software/spice/spice-request.htm and
perform the instructions that appear.
2. In the Simulation Kits table, on the Virtex-II Pro Signal Integrity
Simulation Kit v3.<version> row, click the sis_kit_v2p.zip link, and
then perform the instructions that appear.
3. In the Simulation Kits table, on the RocketIO Design Kit for Mentor
Graphics HyperLynx row, click the available from Mentor Graphics link,
and then perform the instructions that appear.
Installing the Xilinx Virtex-II Pro Signal Integrity Simulation Kit
===================================================================
Perform the following steps:
1. Install the Xilinx Virtex-II Pro Signal Integrity Simuluation Kit
by unzipping sis_kit_v2p.zip to a permanent model folder on the
computer.
Requirements:
a. The folder path cannot contain spaces for Eldo or HSPICE.
b. Preserve the folder structure in the ZIP file. If you are using
WinZip(R), on the Extract dialog box, select the
"Use folder names" check box.
2. Using Windows Explorer, browse to the files you extracted in the
previous step. Locate the folder containing the \IC_models
sub-folders, for example, C:\<folder_name>\sis_kit_v2p_v3.7.
Tip: Write down or memorize this folder name because you will
specify it when installing the RocketIO Design Kit for HyperLynx.
Installing the RocketIO Design Kit for HyperLynx
================================================
Perform the following steps:
1. If HyperLynx is running, close it.
2. Unzip HL_Xilinx_Kit_V.3.7.zip to a temporary folder on the computer.
Requirement: Preserve the folder structure in the ZIP file. If you
are using WinZip(R), on the Extract dialog box, select the "Use
folder names" check box.
Tip: You can remove the unzipped files after you run the HyperLynx
RocketIO Design Kit installation.
3. Using Windows Explorer, browse to the folder you specified in the
previous step and double-click the Install_HypSisKit.exe
application. The HyperLynx RocketIO Design Kit installation dialog
box opens.
4. In the SPICE Simulator area, click the name of the simulator you
will use to simulate the design kit files.
5. In the Prerequisite Software area, do the following as needed:
- Verify the boxes contain the correct folders.
- If a box is blank, or contains an incorrect folder, browse to
the folder containing the software or design kit files, and
then click OK.
Tips:
- For expected folder locations and other installation status
information, see the read-only boxes.
- For the Xilinx Virtex-II Pro Signal Integrity Simulation Kit,
browse to the folder containing the \IC_models sub-folders,
for example C:\<folder_name>\sis_kit_v2p_v3.7.
6. Click Install HyperLynx RocketIO Design Kit to complete the
installation.
Results:
- HyperLynx is configured to use the models and schematics in
the Xilinx Virtex-II Pro Signal Integrity Simulation Kit
folder.
- The following files are copied to the \Example\Hyp_bp folder
under the Xilinx Virtex-II Pro Signal Integrity Simulation
Kit folder, for example
C:\<folder_name>\sis_kit_v2p_v3.7\Example\Hyp_bp:
readme.txt (this file)
RocketIO Design Kit for HyperLynx User Guide (Eldo or HSPICE).pdf
(usage instructions)
rocketio_bp.tln
rocketio_chp_to_chp.tln
TXX.inc
Xilinx_Eldo.inc or Xilinx_HSPICE.inc
- The following file is written to the HyperLynx application
folder. For example C:\HyperLynx72.
Bsw.mask
- If you are using Eldo, the following files are written to the
\Pkg_models folder under the Xilinx Virtex-II Pro Signal Integrity
Simulation Kit folder, for example
C:\<folder_name>\sis_kit_v2p_v3.7\Pkg_models.
ff1152_min.pls
ff1152_max.pls
7. Click Quit to close the HyperLynx RocketIO Design Kit
installation dialog box.
8. If you install the Eldo -and- HSPICE versions of the RocketIO Design
Kit for HyperLynx, note that Eldo cannot simulate models encrypted
for HSPICE (and vice versa). Each time you want to simulate with one
of the SPICE simulators, make sure the folders containing the
encrypted models for that SPICE simulator have higher precedence
than the folders containing the encrypted models for the other SPICE
simulator.
To set model library precedence, do the following in HyperLynx:
a. On the Options menu, click Directories.
b. On the Set Directories dialog box, click the Edit button next to
the Model-library file path list.
c. Select the folder containing the encrypted models for the SPICE
simulator you plan to use, and click the Up button as needed to
position the folder above the folders containing encrypted models
for the other SPICE simulator.
d. Repeat step c as needed for the other folders containing encrypted
models.
e. Click OK to close each dialog box.
Running LineSim to simul
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基 于HyperLynx 9·0的信号 与 电源完整性 仿真分析 光盘文件.zip (572个子文件)
RAM_MODULE_COMPLETE.b02 15KB
add_in_card.b03 3KB
add_in_card.b04 3KB
add_in_card.b05 3KB
HyperLynxIcModels.bak 528KB
HyperLynxIcModels.bak 528KB
HyperLynxIcModels.bak 18KB
HyperLynxIcModels.bak 16KB
add_in_card.bb3 3KB
add_in_card.bb4 3KB
add_in_card.bb5 3KB
MT16HTF6464AY-40EB2_2.bbd 53KB
MT16HTF6464AY-40EB2_1.bbd 52KB
mbd.bbd 4KB
add_in_card.bbd 2KB
MBD.bbd 2KB
Riser_Card.bbd 2KB
toggle_50bits.bit 50B
50_bit_main.bit 50B
TMDS_stimulus.bit 39B
MT16HTF6464AY-40EB2_2.bud 53KB
MT16HTF6464AY-40EB2_1.bud 52KB
post_decoupling_caps_qpl.bud 21KB
RAM_MODULE_COMPLETE.bud 13KB
HYPERLYNX_CLASS_FINAL_BLZ.bud 5KB
mbd.bud 4KB
MBD.bud 3KB
add_in_card.bud 2KB
Riser_Card.bud 2KB
MT16HTF6464AY-40EB2.bud 2KB
libfile_eldo_123.cir 18KB
hsd8ab.cir 14KB
hsd8de.cir 14KB
hsd8gh.cir 14KB
hsd6ab.cir 14KB
hsd6de.cir 14KB
hsd5ab.cir 14KB
hsd5de.cir 14KB
net-DQS_P0_drv-U1_B00.AM8&AM7_rcv-U19_B02.J7&H8_W2.csv 799KB
net-DQS_P0_drv-U1_B00.AM8&AM7_rcv-U1_B02.J7&H8_W2.csv 799KB
net-DQS_P0_drv-U1_B00.AM8&AM7_rcv-U19_B01.J7&H8_W1.csv 799KB
net-DQS_P0_drv-U1_B00.AM8&AM7_rcv-U1_B01.J7&H8_W1.csv 799KB
net-DQS_P0_drv-U1_B00.AM8&AM7_W2.csv 798KB
net-DQS_P0_drv-U1_B00.AM8&AM7_W1.csv 798KB
net-DQS_P0_drv-U1_B02.J7&H8_rcv-U1_B00.AM8&AM7_R2_1_after_shift.csv 798KB
net-DQS_P0_drv-U19_B02.J7&H8_rcv-U1_B00.AM8&AM7_R2_2_after_shift.csv 798KB
net-DQS_P0_drv-U1_B01.J7&H8_rcv-U1_B00.AM8&AM7_R1_1_after_shift.csv 798KB
net-DQS_P0_drv-U19_B01.J7&H8_rcv-U1_B00.AM8&AM7_R1_2_after_shift.csv 798KB
net-DQS_P0_drv-U19_B02.J7&H8_R2_2_before_shift.csv 798KB
net-DQS_P0_drv-U19_B02.J7&H8_R2_2_after_shift.csv 798KB
net-DQS_P0_drv-U19_B01.J7&H8_R1_2_after_shift.csv 798KB
net-DQS_P0_drv-U1_B01.J7&H8_R1_1_before_shift.csv 798KB
net-DQS_P0_drv-U19_B01.J7&H8_R1_2_before_shift.csv 798KB
net-DQS_P0_drv-U1_B01.J7&H8_R1_1_after_shift.csv 798KB
net-DQS_P0_drv-U1_B02.J7&H8_R2_1_after_shift.csv 798KB
net-DQS_P0_drv-U1_B02.J7&H8_R2_1_before_shift.csv 798KB
net-DQS_P0_drv-U19_B01.J7&H8_rcv-U1_B00.AM8&AM7_R1_2_before_shift.csv 798KB
net-DQS_P0_drv-U1_B01.J7&H8_rcv-U1_B00.AM8&AM7_R1_1_before_shift.csv 798KB
net-DQS_P0_drv-U1_B02.J7&H8_rcv-U1_B00.AM8&AM7_R2_1_before_shift.csv 798KB
net-DQS_P0_drv-U19_B02.J7&H8_rcv-U1_B00.AM8&AM7_R2_2_before_shift.csv 798KB
HyperLynxIcModels.csv 543KB
net-CK_P4_drv-U1_B00.AC5&AB5_rcv-U19_B02.M8&N8_W1.csv 491KB
net-CK_P4_drv-U1_B00.AC5&AB5_rcv-U1_B02.M8&N8_W1.csv 491KB
net-CK_P4_drv-U1_B00.AC5&AB5_W1.csv 490KB
net-CK_P1_drv-U1_B00.Y8&Y7_rcv-U19_B01.M8&N8_W1.csv 393KB
net-CK_P1_drv-U1_B00.Y8&Y7_rcv-U1_B01.M8&N8_W1.csv 393KB
net-CK_P1_drv-U1_B00.Y8&Y7_W1.csv 392KB
net-DQ0_drv-U19_B02.L1_R2_2.csv 178KB
net-DQ0_drv-U1_B02.L9_R2_1.csv 178KB
net-DQ0_drv-U1_B01.L9_R1_1.csv 177KB
net-DQ0_drv-U19_B01.L1_R1_2.csv 177KB
net-DQ0_drv-U1_B02.L9_rcv-U1_B00.AR4_R2_1.csv 177KB
net-DQ0_drv-U1_B00.AR4_W2.csv 177KB
net-DQ0_drv-U1_B00.AR4_rcv-U19_B02.L1_W2.csv 177KB
net-DQ0_drv-U19_B01.L1_rcv-U1_B00.AR4_R1_2.csv 177KB
net-DQ0_drv-U1_B00.AR4_rcv-U19_B01.L1_W1.csv 177KB
net-DQ0_drv-U1_B00.AR4_W1.csv 177KB
net-DQ0_drv-U1_B01.L9_rcv-U1_B00.AR4_R1_1.csv 177KB
net-DQ0_drv-U19_B02.L1_rcv-U1_B00.AR4_R2_2.csv 177KB
net-DQ0_drv-U1_B00.AR4_rcv-U1_B02.L9_W2.csv 177KB
net-DQ0_drv-U1_B00.AR4_rcv-U1_B01.L9_W1.csv 177KB
5.csv 35KB
HyperLynxIcModels.csv 18KB
HyperLynxIcModels.csv 18KB
HyperLynxIcModels.csv 15KB
HyperLynxIcModels.csv 13KB
post_decoupling.dao 1KB
2.5V&1.8V.dcs 775B
nonet.dcs 154B
post_dc_drop.dcs 152B
Ip5V.dcs 149B
NewMultipleBoardProject.ddr 11KB
PRBS_2p5ns_bo5.eds 304B
Ip5V.ffs 11.06MB
nonet.ffs 9.17MB
memory_diff_strobe_xtalk.ffs 63KB
DDR_4DIMM_address_min.ffs 51KB
DDR_4DIMM_address_max.ffs 51KB
dq_with_diff_dqs.ffs 38KB
memory_single_ended_dq_xtalk.ffs 37KB
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资源评论
- licfu2021-06-25是我想找打光盘资源,3Q!
- li__xue2021-03-25没有书,我还以为是包含《基于HyperLynx 9.0的信号与电源完整性仿真分析》这本书的资料了,感觉被骗了阴阳万物2021-04-07你也可以下载 HyperLynx三合一阴阳万物2021-04-07文件名称就已经写明了,光盘文件,里面包含案例分析
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