# EGo1-Vivado-Lock
FPGA设计，借助Vivado和Ego1实验平台设计的密码锁[内附报告]（FPGA design, password lock designed by vivado and ego1 experimental platform [attached report]）
## 实验环境
- 操作系统：Window 10；
- 设计软件：Vivado 2017.4；
- 硬件平台：Ego1；
## 实现功能
- 准备解锁时，显示 CALL 字符等待输入
- 成功解锁
- 调节按钮 SW7（左下角按钮上拉，相应 LED 点亮，流水灯切换为间隔亮灯）， 此时调节每位密码数值设置锁的密码
- 设置完后返回正常解锁模式测试，输入 1234 成功解锁，返回-HCC
- 超过 20 秒未输入正确密码，密码锁将锁死，返回 FAIL
## 详细介绍
- 见[实验报告](./移动通信网络实验报告.pdf)
© JackHCC
Verilog FPGA设计数字密码锁
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2022-03-15
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Verilog FPGA设计数字密码锁 （212个子文件） 
__synthesis_is_complete__ 0B runme.bat 229B runme.bat 229B lock.bit 2.09MB lock_routed.dcp 2.61MB lock_placed.dcp 2.03MB lock_opt.dcp 1.05MB lock.dcp 994KB
usage_statistics_webtalk.html 31KB vivado.jou 856B vivado.jou 721B vivado.jou 717B ISEWrap.js 8KB ISEWrap.js 8KB rundef.js 1KB rundef.js 1KB runme.log 30KB runme.log 28KB vivado.log 2KB lock.lpr 335B README.md 927B vivado.pb 48KB place_design.pb 17KB route_design.pb 14KB opt_design.pb 11KB write_bitstream.pb 4KB init_design.pb 3KB lock_power_summary_routed.pb 723B lock_utilization_synth.pb 242B lock_utilization_placed.pb 242B vivado.pb 149B lock_timing_summary_routed.pb 109B lock_methodology_drc_routed.pb 52B lock_route_status.pb 44B lock_drc_routed.pb 37B lock_drc_opted.pb 37B lock_bus_skew_routed.pb 30B
数字密码锁.pdf 1.42MB
Unlock.png 811KB Call.png 718KB ChangeDone.png 585KB Fail.png 570KB Change.png 508KB lock_timing_summary_routed.rpt 166KB lock_io_placed.rpt 97KB lock_clock_utilization_routed.rpt 12KB lock_utilization_placed.rpt 9KB lock_methodology_drc_routed.rpt 8KB lock_power_routed.rpt 7KB lock_utilization_synth.rpt 7KB lock_control_sets_placed.rpt 5KB lock_drc_routed.rpt 2KB lock_drc_opted.rpt 2KB lock_bus_skew_routed.rpt 839B lock_route_status.rpt 588B lock_power_routed.rpx 1.84MB lock_timing_summary_routed.rpx 160KB lock_methodology_drc_routed.rpx 33KB lock_drc_routed.rpx 2KB lock_drc_opted.rpx 2KB lock_bus_skew_routed.rpx 1001B .vivado.begin.rst 217B .vivado.begin.rst 217B .write_bitstream.begin.rst 178B .init_design.begin.rst 178B .place_design.begin.rst 178B .route_design.begin.rst 178B .opt_design.begin.rst 178B .route_design.end.rst 0B .vivado.end.rst 0B .opt_design.end.rst 0B .write_bitstream.end.rst 0B .Vivado_Implementation.queue.rst 0B .place_design.end.rst 0B .Vivado_Synthesis.queue.rst 0B .init_design.end.rst 0B .vivado.end.rst 0B ISEWrap.sh 2KB ISEWrap.sh 2KB runme.sh 1KB runme.sh 1KB lock.tcl 6KB lock.tcl 3KB
htr.txt 393B htr.txt 385B README.txt 129B lock.v 13KB clock_make.v 5KB digital_put.v 2KB lock.vdi 30KB lock.vds 28KB gui_handlers.wdf 9KB synthesis.wdf 5KB project.wdf 4KB java_command_handlers.wdf 3KB synthesis_details.wdf 100B project.wpc 122B lock_propImpl.xdc 6KB vtf_lock.xdc 4KB usage_statistics_webtalk.xml 45KB共 212 条
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