################################################################################
# Vivado (TM) v2018.3 (64-bit)
#
# README.txt: Please read the sections below to understand the steps required
# to simulate the design for a simulator, the directory structure
# and the generated exported files.
#
################################################################################
1. Simulate Design
To simulate design, cd to the simulator directory and execute the script.
For example:-
% cd questa
% ./top.sh
The export simulation flow requires the Xilinx pre-compiled simulation library
components for the target simulator. These components are referred using the
'-lib_map_path' switch. If this switch is specified, then the export simulation
will automatically set this library path in the generated script and update,
copy the simulator setup file(s) in the exported directory.
If '-lib_map_path' is not specified, then the pre-compiled simulation library
information will not be included in the exported scripts and that may cause
simulation errors when running this script. Alternatively, you can provide the
library information using this switch while executing the generated script.
For example:-
% ./top.sh -lib_map_path /design/questa/clibs
Please refer to the generated script header 'Prerequisite' section for more details.
2. Directory Structure
By default, if the -directory switch is not specified, export_simulation will
create the following directory structure:-
<current_working_directory>/export_sim/<simulator>
For example, if the current working directory is /tmp/test, export_simulation
will create the following directory path:-
/tmp/test/export_sim/questa
If -directory switch is specified, export_simulation will create a simulator
sub-directory under the specified directory path.
For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim'
command will create the following directory:-
/tmp/test/my_test_area/func_sim/questa
By default, if -simulator is not specified, export_simulation will create a
simulator sub-directory for each simulator and export the files for each simulator
in this sub-directory respectively.
IMPORTANT: Please note that the simulation library path must be specified manually
in the generated script for the respective simulator. Please refer to the generated
script header 'Prerequisite' section for more details.
3. Exported script and files
Export simulation will create the driver shell script, setup files and copy the
design sources in the output directory path.
By default, when the -script_name switch is not specified, export_simulation will
create the following script name:-
<simulation_top>.sh (Unix)
When exporting the files for an IP using the -of_objects switch, export_simulation
will create the following script name:-
<ip-name>.sh (Unix)
Export simulation will create the setup files for the target simulator specified
with the -simulator switch.
For example, if the target simulator is "ies", export_simulation will create the
'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib'
file.
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FPGA FIR低通数字滤波器 (664个子文件)
__synthesis_is_complete__ 0B
runme.bat 229B
runme.bat 229B
AD_top.bit 3.86MB
tb_fir_compiler_0.c 8KB
tb_fir_compiler_0.c 8KB
untitled.coe 412B
untitled.coe 412B
untitled.coe 412B
untitled.coe 412B
untitled.coe 412B
untitled.coe 412B
untitled.coe 412B
untitled.coe 412B
untitled.coe 412B
untitled.coe 412B
u_ila_0.dcp 687KB
u_ila_0.dcp 631KB
AD_top_routed.dcp 444KB
AD_top_placed.dcp 415KB
dbg_hub.dcp 347KB
AD_top_opt.dcp 344KB
fir_compiler_0.dcp 175KB
fir_compiler_0.dcp 175KB
AD_top.dcp 138KB
fir_compiler_0.dcp 123KB
fir_compiler_0.dcp 123KB
fir_compiler_0.dcp 123KB
fir_compiler_0.dcp 84KB
xadc_wiz_0.dcp 11KB
xadc_wiz_0.dcp 11KB
xadc_wiz_0.dcp 10KB
clk_wiz_0.dcp 9KB
clk_wiz_0.dcp 9KB
clk_wiz_0.dcp 9KB
clk_wiz_0.dcp 9KB
compile.do 1KB
compile.do 1KB
compile.do 1KB
compile.do 1KB
compile.do 675B
compile.do 651B
compile.do 610B
compile.do 600B
compile.do 550B
compile.do 526B
compile.do 485B
compile.do 475B
simulate.do 386B
simulate.do 386B
simulate.do 386B
simulate.do 313B
simulate.do 311B
simulate.do 309B
simulate.do 309B
simulate.do 306B
simulate.do 306B
elaborate.do 258B
simulate.do 205B
simulate.do 197B
simulate.do 195B
elaborate.do 185B
elaborate.do 183B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
simulate.do 11B
simulate.do 11B
simulate.do 11B
run.f 729B
run.f 701B
run.f 462B
run.f 446B
run.f 389B
run.f 373B
fir_compiler_0.h 5KB
fir_compiler_0.h 4KB
usage_statistics_webtalk.html 32KB
hw_ila_data_1.ila 141KB
xsim.ini 22KB
xsim.ini 22KB
xsim.ini 22KB
vivado_14268.backup.jou 50KB
vivado_5008.backup.jou 6KB
vivado_4896.backup.jou 4KB
vivado_22120.backup.jou 4KB
vivado_14364.backup.jou 800B
vivado.jou 798B
vivado.jou 754B
vivado_14876.backup.jou 754B
vivado_12688.backup.jou 754B
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