################################################################################
# Vivado (TM) v2019.2 (64-bit)
#
# README.txt: Please read the sections below to understand the steps required
# to simulate the design for a simulator, the directory structure
# and the generated exported files.
#
################################################################################
1. Simulate Design
To simulate design, cd to the simulator directory and execute the script.
For example:-
% cd questa
% ./top.sh
The export simulation flow requires the Xilinx pre-compiled simulation library
components for the target simulator. These components are referred using the
'-lib_map_path' switch. If this switch is specified, then the export simulation
will automatically set this library path in the generated script and update,
copy the simulator setup file(s) in the exported directory.
If '-lib_map_path' is not specified, then the pre-compiled simulation library
information will not be included in the exported scripts and that may cause
simulation errors when running this script. Alternatively, you can provide the
library information using this switch while executing the generated script.
For example:-
% ./top.sh -lib_map_path /design/questa/clibs
Please refer to the generated script header 'Prerequisite' section for more details.
2. Directory Structure
By default, if the -directory switch is not specified, export_simulation will
create the following directory structure:-
<current_working_directory>/export_sim/<simulator>
For example, if the current working directory is /tmp/test, export_simulation
will create the following directory path:-
/tmp/test/export_sim/questa
If -directory switch is specified, export_simulation will create a simulator
sub-directory under the specified directory path.
For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim'
command will create the following directory:-
/tmp/test/my_test_area/func_sim/questa
By default, if -simulator is not specified, export_simulation will create a
simulator sub-directory for each simulator and export the files for each simulator
in this sub-directory respectively.
IMPORTANT: Please note that the simulation library path must be specified manually
in the generated script for the respective simulator. Please refer to the generated
script header 'Prerequisite' section for more details.
3. Exported script and files
Export simulation will create the driver shell script, setup files and copy the
design sources in the output directory path.
By default, when the -script_name switch is not specified, export_simulation will
create the following script name:-
<simulation_top>.sh (Unix)
When exporting the files for an IP using the -of_objects switch, export_simulation
will create the following script name:-
<ip-name>.sh (Unix)
Export simulation will create the setup files for the target simulator specified
with the -simulator switch.
For example, if the target simulator is "ies", export_simulation will create the
'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib'
file.
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温馨提示
1.版本:vivado2019.2,matlab2022A。 2.包含:程序,中文注释,参考文献,仿真操作步骤(使用windows media player播放)。 3.领域:FIR低通滤波器 4.仿真效果:仿真效果可以参考博客同名文章《基于FPGA的FIR低通滤波器verilog实现,包含testbench和滤波器系数计算matlab程序》 5.内容:基于FPGA的FIR低通滤波器verilog实现,包含testbench和滤波器系数计算matlab程序。基于FPGA实现FIR(Finite Impulse Response)低通滤波器时,通常分为两个主要步骤:使用MATLAB计算滤波器系数,然后使用Verilog语言在FPGA上实现这些系数。测试文件,使用2个高低频的正弦输入,滤波得到低频正弦信号。 6.注意事项:注意FPGA的路径必须是英文,路径字母长度小于148
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基于FPGA的FIR低通滤波器verilog实现,包含testbench【包括程序,注释,参考文献,操作步骤】 (342个子文件)
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
xsim.ini.bak 26KB
elaborate.bat 2KB
compile.bat 972B
simulate.bat 888B
runme.bat 229B
runme.bat 229B
xsim_1.c 18KB
xsim.dbg 12KB
dds_compiler_1.dcp 57KB
dds_compiler_1.dcp 57KB
dds_compiler_1.dcp 57KB
dds_compiler_1.dcp 57KB
dds_compiler_1.dcp 57KB
dds_compiler_1.dcp 57KB
dds_compiler_0.dcp 46KB
dds_compiler_0.dcp 46KB
dds_compiler_0.dcp 46KB
dds_compiler_0.dcp 46KB
dds_compiler_0.dcp 46KB
dds_compiler_0.dcp 46KB
compile.do 2KB
compile.do 2KB
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simulate.do 479B
simulate.do 479B
simulate.do 479B
simulate.do 479B
simulate.do 479B
simulate.do 479B
elaborate.do 351B
elaborate.do 351B
simulate.do 205B
simulate.do 205B
wave.do 12B
wave.do 12B
wave.do 12B
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wave.do 12B
simulate.do 11B
simulate.do 11B
xsimk.exe 440KB
run.f 1KB
run.f 1KB
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usage_statistics_ext_xsim.html 3KB
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xsim.ini 26KB
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xsim.ini 26KB
xsimSettings.ini 1KB
webtalk.jou 898B
webtalk_40476.backup.jou 898B
vivado.jou 796B
vivado.jou 796B
ISEWrap.js 8KB
ISEWrap.js 8KB
rundef.js 1KB
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runme.log 31KB
flex648.log 6KB
flex652.log 6KB
elaborate.log 1KB
webtalk_40476.backup.log 967B
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xsimcrash.log 0B
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project_1.lpr 290B
runme.m 281B
xsim.mem 434KB
操作步骤.mp4 8.06MB
xsim_0.win64.obj 395KB
xsim_1.win64.obj 13KB
elab.opt 363B
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