*************************************************************************
____ ____
/ /\/ /
/___/ \ /
\ \ \/ � Copyright 2012 - 2014 Xilinx, Inc. All rights reserved.
\ \ This file contains confidential and proprietary
/ / information of Xilinx, Inc. and is protected under U.S.
/___/ /\ and international copyright and other intellectual
\ \ / \ property laws.
\___\/\___\
*************************************************************************
Vendor: Xilinx
Current readme.txt Version: 2.1
Date Last Modified: 24JUL2014
Date Created: 09AUG2012
Associated Filename: xapp592.zip
Associated Document: XAPP592, Implementing SMPTE SDI Interfaces with Kintex-7 GTX Transceivers
Supported Device(s): Kintex-7 FPGAs
*************************************************************************
Disclaimer:
This disclaimer is not a license and does not grant any rights to
the materials distributed herewith. Except as otherwise provided in
a valid license issued to you by Xilinx, and to the maximum extent
permitted by applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE
"AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL
WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
(2) Xilinx shall not be liable (whether in contract or tort,
including negligence, or under any other theory of liability) for
any loss or damage of any kind or nature related to, arising under
or in connection with these materials, including for any direct, or
any indirect, special, incidental, or consequential loss or damage
(including loss of data, profits, goodwill, or any type of loss or
damage suffered as a result of any action brought by a third party)
even if such damage or loss was reasonably foreseeable or Xilinx
had been advised of the possibility of the same.
Critical Applications:
Xilinx products are not designed or intended to be fail-safe, or
for use in any application requiring fail-safe performance, such as
life-support or safety devices or systems, Class III medical
devices, nuclear facilities, applications related to the deployment
of airbags, or any other applications that could lead to death,
personal injury, or severe property or environmental damage
(individually and collectively, "Critical Applications"). Customer
assumes the sole risk and liability of any use of Xilinx products
in Critical Applications, subject only to applicable laws and
regulations governing limitations on product liability.
THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS
FILE AT ALL TIMES.
*************************************************************************
This readme file contains these sections:
1. REVISION HISTORY
2. OVERVIEW
3. SOFTWARE TOOLS AND SYSTEM REQUIREMENTS
4. DESIGN FILE HIERARCHY
5. INSTALLATION AND OPERATING INSTRUCTIONS
6. OTHER INFORMATION
7. SUPPORT
1. REVISION HISTORY
Readme
Date Version Revision Description
=========================================================================
09AUG2012 1.0 Initial Xilinx release.
16OCT2012 1.1 Fixed typos in readme.txt file only. No changes
to any other files.
17DEC2012 1.2 Made changes to the DRP controller in the SDI wrapper to
insure that it correctly writes to the GTX through the
DRP to change the RXCDR_CFG attribute dynamically.
Created new GTX wrappers for the demos using v2.4 of the
GTX wizard. Version 2.4 of the GTX wizard produces GTX
wrappers with a slightly different set of ports, so the
demos were updated to match the new GTX wrappers.
10JUL2014 2.0 The GTX wrappers generated by versions 3.0 and later of
the transceiver wizard differ in very fundamental ways
from wrappers created by earlier versions of the wizard.
The SD/HD/3G-SDI core version 3.0 also has some port
name changes from earlier versions of the core as required
to comply with port naming standards for Xilinx IP. The SDI
wrapper files have been updated to support these changes
and to align the control logic and wrappers with the GTP
and GTH SDI wrappers. All demo files have been updated
to match these changes. VHDL versions of wrappers and
demos have been removed. And, the app note now targets
Vivado only. The code supplied here is compatible with
Version 3.3 of the 7 Series FPGAs Transceivers Wizard
that ships in Vivado 2014.2.
24JUL2014 2.1 With current Vivado synthesis, the ST 352 payload ID
state machine in the SDI RX is susceptible to becoming
stuck in an invalid state while the GTX RX is changing
between SDI modes. The SDI wrapper has been modified to
reset the SDI RX while the GTX RX is changing modes.
=========================================================================
2. OVERVIEW
This readme describes how to use the files that come with XAPP592.
There are two example SDI designs provided with XAPP592.
One design has four SDI receivers and four SDI transmitters. The receivers and
transmitters are all independent of each other. The SDI transmitters are driven
by video pattern generators. The data received by the SDI receivers is captured
by ChipScope Pro modules.
The other design is a single channel SDI pass-through configuration where the
SDI transmitter retransmits the signal received by the SDI receiver.
3. SOFTWARE TOOLS AND SYSTEM REQUIREMENTS
* Vivado 2013.4 or newer
4. DESIGN FILE HIERARCHY
The directory structure underneath this top-level folder is described
below:
\bit_files
| This folder contains FPGA configuration bit files for the demos included
| in this release.
|
\chipscope_projects
| This folder contains project files for ChipScope Pro analyzer,
| one .cpj file for each of the demos included in this release.
|
\dru
| This directory contains the data recovery unit (DRU) code required
| to receive 270 Mb/s SD-SDI. The dru.ngc file contains the pre-
| synthesized DRU IP. It must be added to the Vivado project along with
| the HDL files in the \dru directory.
| +--\for_simulation_only
| This directory contains a simple model of the DRU that can be
| used for simulation. The dru.ngc file cannot be simulated due to
| encryption of the file. The simulation model must not, however,
| be used in an actual FPGA configuration because it does not have
| any jitter tolerance.
|
\k7gtx_sdi_wrapper
| This directory contains the GTX wrapper and GTXE2_COMMON wrapper files
| generated by the GTX wizard specifically for these demos.
|
\kc705_sdi_demo
| This directory contains the HDL and other files unique to the quad
| SDI demo.
|
\kc705_sdi_pass_demo
| This directory contains the HDL and other files unique to the SDI
| pass-through demo.
|
\kc705_TEDSDI_control
| This directory contains the HDL and other files that are used by
| both demos to control devices on the KC705 and
没有合适的资源?快使用搜索试试~ 我知道了~
xilinx app592 demo
共78个文件
v:47个
xdc:13个
ngc:10个
需积分: 0 9 下载量 90 浏览量
2023-10-10
17:36:52
上传
评论 1
收藏 3.22MB ZIP 举报
温馨提示
直接上传,C-S-D-N不让上传,只能重新压缩了一下,才可以上传
资源推荐
资源详情
资源评论
收起资源包目录
xapp592_sdi.zip (78个子文件)
xapp592_sdi
xapp592-smpte-sdi-w-k7-gtx-transceivers.pdf 2.74MB
xapp592_ver2_1
bit_files
kc705_sdi_pass.bit 10.91MB
kc705_sdi_demo.bit 10.91MB
k7gtx_sdi_wrapper
k7gtx_sdi_wrapper_gt.v 45KB
k7gtx_sdi_wrapper_common.v 10KB
k7gtx_sdi_wrapper_sync_block.v 5KB
SDI_wrapper
sdi_rate_detect.v 14KB
sdi_control_sync_block.v 4KB
x7gtx_sdi_tx_control_fsm.v 18KB
x7gtx_sdi_tx_control.v 12KB
x7gtx_sdi_rx_reset_control.v 15KB
x7gtx_sdi_wrapper.v 26KB
x7gtx_sdi_drp_control.v 19KB
x7gtx_sdi_tx_sequence.v 11KB
x7gtx_sdi_control.v 14KB
kc705_TEDSDI_control
k7_sdi_demo_name.txt 320B
lcd_control5.v 10KB
kcpsm3.v 48KB
kcpsm6.v 81KB
lmh0387t.v 22KB
LCDAUX5.V 9KB
LCDCTRL5.V 9KB
LMH0387_control.v 7KB
kc705_sdi_demo
vidgen_ntsc.v 98KB
kc705_sdi_demo_timing.xdc 2KB
vidgen_pal.v 98KB
kc705_sdi_demo.v 21KB
multigenHD.v 13KB
k7_sdi_rxtx.v 21KB
chipscope
tx_vio.ngc 56KB
rx_vio.xdc 69B
vio0.ngc 27KB
rx_ila.xdc 477B
icon.xdc 793B
rx_ila.v 941B
rx_vio.v 988B
rx_ila.ngc 544KB
icon.v 1KB
tx_vio.xdc 69B
icon.ngc 148KB
rx_vio.ngc 200KB
vio0.v 920B
vio0.xdc 80B
tx_vio.v 1KB
kc705_sdi_demo.xdc 6KB
multigenHD_horz.v 26KB
multigenHD_vert.v 24KB
multigenHD_output.v 21KB
dru
dru.ngc 523KB
dru_maskencoder.v 5KB
dru_control.v 4KB
dru_bshift10to10.v 5KB
dru_rot20.v 4KB
dru.v 4KB
for_simulation_only
dru_sim.v 5KB
kc705_sdi_pass_demo
kc705_sdi_pass_demo_timing.xdc 1KB
kc705_sdi_pass.v 20KB
KCSi5324.v 22KB
chipscope
vio.v 918B
rx_vio.xdc 69B
vio.xdc 80B
icon.xdc 793B
rx_vio.v 988B
icon.v 964B
ila.v 935B
icon.ngc 50KB
ila.ngc 544KB
rx_vio.ngc 200KB
ila.xdc 477B
vio.ngc 22KB
Si5324_settings_rom_v1_5.coe 21KB
kc705_sdi_pass_demo.xdc 5KB
Si5324_fsel_lookup.v 5KB
kc705_Si5324_control.v 9KB
k7_sdi_pass.v 22KB
readme.txt 30KB
chipscope_projects
kc705_sdi_demo.cpj 365KB
kc705_sdi_pass.cpj 85KB
共 78 条
- 1
资源评论
UKR_FPGA_LY
- 粉丝: 13
- 资源: 3
上传资源 快速赚钱
- 我的内容管理 展开
- 我的资源 快来上传第一个资源
- 我的收益 登录查看自己的收益
- 我的积分 登录查看自己的积分
- 我的C币 登录后查看C币余额
- 我的收藏
- 我的下载
- 下载帮助
最新资源
- vscode-1.64.1.tar源码文件
- vscode-1.64.0.tar源码文件
- vscode-1.52.0.tar源码文件
- Music-Player +PlayerActivity+ rockplayer+ SeeJoPlayer 播放器JAVA源码
- vscode-1.46.0.tar源码文件
- 最近很火植物大战僵尸杂交版2.08苹果+安卓+PC+防闪退工具V2+修改工具+高清工具+通关存档整合包更新
- 超级好用的截图工具PixPin,可录制Gif图
- Screenshot_2024-05-21-17-06-42-64_2332cb9b27b851b548ba47a91682926c.jpg
- 毕业设计参考 - 基于树莓派、OpenCV及Python的人脸识别
- node-v18.20.2-linux-arm64
资源上传下载、课程学习等过程中有任何疑问或建议,欢迎提出宝贵意见哦~我们会及时处理!
点击此处反馈
安全验证
文档复制为VIP权益,开通VIP直接复制
信息提交成功