3G_SDI_Demo_Board_Xilinx_Version

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3G_SDI_Demo_Board_Xilinx_Version The 3Gb/s SDI Demo Board is designed to demonstrate the functionality, flexibility and implementation simplicity of Gennum’s 3G/HD/SD SDI devices. The Demo Kit consists of a 3Gb/s SDI Demo Board, FPGA source code and PC software. Paired with an additional Xilinx Spar
3.5.5 JTAG Programming(2) 19 4. Getting Started 4.1 Quick Start Guide 4.2 FPGA Configuration 4.2.1 TAG Direct........... 47.2 SPI PROM ,,,,4 5. Advanced User Guide 5.1 Top Level architecture. 5.2 Clock tree and data path 5.3 Pattern generator 24 5.3.1 Top Level Architecture 5.3.2 Reset Network 25 5.3.3 Clock Generator 5.3.4 Colour Bar generator 5.35 20b to 10b mux 5.4 Optical Module............... 5.5 Data path “·↓ 5.6 1/0 Timing Closure… 31 5.7 Clock termination∴ 5. 8 FPGA User Constraints 5.8.1 Input Data Window Specification 5.8.2 Internal Clock constraints 5.8.3 MAXDELAY Constraints 5.8.1 Location constraints 6 33 5.8.5 Non-Clock Dedicated route. “=+=+++“““=+““- 34 5.8.6 Input Delay Adjustment..... 34 587 Output Timing Adjustment………… 34 5.9 Host Interface and Register Map 5.10 Suggestions 35 6. Related Documents 6.1 Gennun' s Documentation…………………… 6.2 Xilinx's documentation 7. Appendix. 7.1 Schematics …37 7.2 Board layout… 1948 7.3 Bill of materials 3Gb/5 SDI Demo board: xilinx Version 3of53 User Guide 52857-1 August 2009 gennum Proprietary Confidential 1 Overview The 3 Gb/s SDI Demo Board is designed to demonstrate the functionality, flexibility and implementation simplicity of Gennum's 3G/HD/SD SDI devices. The Demo Kit consists of a 3Gb/s sdi demo board fPga source code and pc software Paired with an dditional Xilinx Spartan-3A DSP 1800A Board, it makes a versatile demo/evaluation platform for Gennum's 3Gb/s products. It is expected to help the users in system design with Gennum 3Gb/s devices The purpose of this document is to describe the functionalities and contents of Gennum's 3Gb/s SDI Demo Board for the Xilinx Spartan- 3A DSP 1800A Board. Also included are a Quick Start Guide and an Advanced User Guide. If a quick start is anticipated, Please go to 4.1 Quick Start Guide. The Schematics, Board Layout and the Bill of Materials are given in the Appendix section at the end of this document 1.1 Features Thrce 3G-SDI inputs with associated GS2974B Equalizers; Two Gcnnum gS2970 Rcccivcrs One 3G-SDI loop-through output Two Gennum gs2970 Transmitters External Sync input followed by a Gennum G$49 11B Clock and Timing generator Provision for a Gennum Go2921 Optical Transceiver (not supplied with the board HSMC Connector interface to Xilinx FPga board Two AES inputs for audio embedding Two AES outputs for audio de-embedding a standard gennum spi header Status indication LEDs and control jumpers Pass-through Mode Dual-Link to 3Gb/s conversion 3Gb/s to dual-Link conversion Stand alone video Test Pattern Generator(Both Genlock or Free-run Audio embedding and de-cmbedding GSPI Daisy Chain 1.2 Featured devices GS2970 SD/HD/3G SDI Receiver complete with SMPTE Audio and Video Processing GS2972 SD/HD/3G SDI Transmitter complete with SMPTE Audio and Video Processing GS2974B Adaptive cable equalizer GS2978 Multi-rate Dual Slew rate Cable driver GS4911B HD/SD/Graphics Clock and Timing Generator with GENLOCK 3Gb/5 SDI Demo board: xilinx Version 4of53 User Guide 52857-1 August 2009 gennum Proprietary Confidential 2 Hardware When you receive the 3 Gb/s SDI Demo board, the kit includes a 3Gb/s sDI Demo board A Gennum Serial Peripheral Interface(GSPT)Dongle Other items to be supplied by the customer A Spartan-3A DSP 1800 Board A PC or laptop with iSE or iMPACT installed (optional) Xilinx Parallel Cable iv or Platform Cable USB Il(optional) 2.1 Gennum 3Gb/s spi demo board Figure 2-1 shows the top side of the 3Gb/s sdi demo board AES Audio Output 1(1) AES Audio output 2 (J2) SDI Loop-through (s) Power status +SDI Input AIN1(3) LED (D1) gennum +SDI Input AIN2(J4) Des lock status (U4, U5) U2- RDK-3GRXTXO-XLNX Source selection(13, 314) S/N JUNE 2009 v MADE IN CANADA SDI Inputs BIN1 (J6 Optical Transceiver Footprint(U30) + SDI Output AOUTn (J8 GSPI Header ( 7) SDI Outputs BOUTn (J9 Ser Lock Status(U13, U14 G S49 11B Lock/Ref Status(U22, U23) Extenal Sync Input(J12) AES Audio Input 2(11) AES Audio Input 1(10) Figure 2-1: Top Side of the 3Gb/s SDI Demo board 3Gb/5 SDI Demo board: xilinx Version 5of53 User Guide 52857-1 August 2009 gennum Proprietary Confidential Figure 2-2 show the bottom side of the 3 Gb/s SDI Demo Board 305-PD-09016 Parallel Connector (JX1) Figure 2-2: Bottom side of the 3 Gb/s SDI Demo board NOTE: The board you receive may not look exactly the same as the board shown in Figure 2-1 and Figure 2-2 in terms of revision code, date code, etc. Figure 2-3 shows the Gennum SPI Dongle Board 时中 于EH Figure 2-3: Gennum SPl Dongle Board +ribbon Cable 3Gb/5 SDI Demo board: xilinx Version 6of53 User Guide 52857-1 August 2009 gennum Proprietary Confidential Figure 2-4 shows a block diagram of the features and signal flows of the 3G/s SDi demo Board AES Audial A Loopback gennum gennum GS2978 ○○○○ GS2970 gennum G52974B PCLK 3Gb/s, HD, SD SDI Receiver EO GSPI Gennum GS2974B o pin control E To Gennum parts Data STAT [0: 4] gennum (gennum GS2970 GS2974B PCLK EQ Serial Audio 3Gb/s, HD. SD SDI Receiver B In ○○○○○○○○○○○○○○○○ gennum Optical Transceiver Footprint PCLK Serial audio gennum GS2972 3Gb/. HD, SD PCLK SDI Transmitter A Out gennum gennum PCLK G54911B GS2972 GSPI In 3Gb/s HD. SD SDI Transmitte B Out EXT Sync AEs Audio B Figure 2-4: Block Diagram of the 3Gb/s SDi Demo board 3Gb/5 SDI Demo board: xilinx Version 7of53 User Guide 52857-1 August 2009 gennum Proprietary Confidential Table 2-1: 3 Gb/s SDI Demo Board Legend Description Label SDI Input ain1 SDI Input ain SDI Input bin1 SDI Output AOUTn SDI Output BOUTn 46897 GSPI Header AES Audio Input 1 J10 AES Audio Input 2 J11 Parallel Connector JX1 SDI Loop-through J5 AES Audio output 1 」1 AES Audio Output 2 」2 Power status led D1 Receiver lock status Indicators U4,U5 Transmitter lock status Indicators U13,U14 Video source selection Jumpers J13,114 External Sync Input J12 GS4911B Lock/Ref status U22.U23 3Gb/5 SDI Demo board: xilinx Version 8of53 User Guide 52857-1 August 2009 gennum Proprietary Confidential 2.2 Xilinx Spartan-3A DSP 1800 Board igure 2-5 shows the Xilinx Spartan-3A DSP 1800A Board. The switches, FPGA, connectors, jumpers, push buttons and LEDs used in this Demo Kit are highlighted in this gure JTAG(2) FPGA (U6) ②6 PWR(SW1) 吗出出 阳日器 5VDC In (J5) RERTT/: SPARTAN-3 HSMC X2 AES-XLX-SP3ADSP-ASY-1 z 酶em Sptrten-3A DSP 1800 Bard ⊙ SPI HDR( 10) D:墨 B 踢删置LED 像③ Hg t XILINX 到Www.xilhx.com/3badspstarte d OP Mode(sw3) 智叫厘男即 要年 FPGA Config Done(D1) PROG B P7) Reset LEd(D6) Reset Button(SW4 LEDS(D7-14 PG Std Pattern(SW5, 6, 7&8) Figure 2-5: Xilinx Spartan -3A DSP 1800A Board 3Gb/5 SDI Demo board: xilinx Version 9of53 User Guide 52857-1 August 2009 gennum Proprietary Confidential 3. Detailed Description This section describes the frequently used devices and their functions. For unused jumpers, switches, LEDs on the FPGA board, please refer to UG485 Getting Started with the Spartan-3A DSP S3 D1800A Starter Platform User Guide 3.1 Switches and Settings 3.1.1 Power Switch(SW1) The PWr(SW1)on the Xilinx Spartan-3A DSP 1800A Board controls the power of the boards 3.1.2 Operating Modes(sw3 Bits 1-3) The current release of the FPGA code supports five distinct modes of operation Pass-through, 3G Level b to Dual-Link, Dual-Link to 3G level B Test Pattern with Genlock and Test Pattern with Free-run modes. The operating mode can be set through a dip switch(SW3 bits 1-3),or by programming the FPGA'sinternalregisters through the SPI Table 3-1 details how the operating mode is selected by the dip switches on the Xilinx board Table 3-1: Operation Modes set by SW3 on Xilinx Board Dip Switch State Operation Mode Notes SW3: Bits 1.2, 3 OFF/OFF/OFF Video Pass-through All standards OFF/OFF/ON 3G Level b to dual-Link ON/OFFOFF Dual-Link to 3G Level B Y CbCr 422 10b. the mon itor set to 1080159.94 ON/ON/OFF Genlock test pattern Selected standards ON/OFF/ON Free-run Test Pattern All standards and patterns SW3: Bits 4-8 Not defined Video pass-through mode: Received video from input a is passed to output A, and input b passed to output b without any process. All SD, HD and 3G formats are supported. For 3G, the default setting is Level A If Level B is anticipated, the configuration for the GS2972 must be changed through the SPI. 3G Level B to Dual-Link mode(HD): 3G Level B video from input a is passed to outputs a and b as a two hd stream output Dual-Link(HD)to 3G Level B mode: Two HD signals, with the same standard, from inputs A and B are multiplexed onto a 10-bit stream and passed to output A. By default, the gs297 2 is configured to output a 3G Level B video signal 3Gb/5 SDI Demo board: xilinx Version 10of53 User Guide 52857-1 August 2009 gennum Proprietary Confidential

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