Release 14.7 - par P.20131013 (nt64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Tue Sep 22 12:04:57 2015
INFO: The IO information is provided in three file formats as part of the Place and Route (PAR) process. These formats are:
1. The <design name>_pad.txt file (this file) designed to provide information on IO usage in a human readable ASCII text format viewable through common text editors.
2. The <design namd>_pad.csv file for use with spreadsheet programs such as MS Excel. This file can also be read by PACE to communicate post PAR IO information.
3. The <design name>.pad file designed for parsing by customers. It uses the "|" as a data field separator.
INPUT FILE: uart_test_map.ncd
OUTPUT FILE: uart_test_pad.txt
PART TYPE: xc6slx16
SPEED GRADE: -3
PACKAGE: csg324
Pinout by Pin Number:
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|Pin Number|Signal Name|Pin Usage|Pin Name |Direction|IO Standard|IO Bank Number|Drive (mA)|Slew Rate|Termination|IOB Delay|Voltage |Constraint|IO Register|Signal Integrity|
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|A1 | | |GND | | | | | | | | | | | |
|A2 | |IOBS |IO_L2N_0 |UNUSED | |0 | | | | | | | | |
|A3 | |IOBS |IO_L4N_0 |UNUSED | |0 | | | | | | | | |
|A4 | |IOBS |IO_L5N_0 |UNUSED | |0 | | | | | | | | |
|A5 | |IOBS |IO_L6N_0 |UNUSED | |0 | | | | | | | | |
|A6 | |IOBS |IO_L8N_VREF_0 |UNUSED | |0 | | | | | | | | |
|A7 | |IOBS |IO_L10N_0 |UNUSED | |0 | | | | | | | | |
|A8 | |IOBS |IO_L33N_0 |UNUSED | |0 | | | | | | | | |
|A9 | |IOBS |IO_L35N_GCLK16_0 |UNUSED | |0 | | | | | | | | |
|A10 | |IOBS |IO_L37N_GCLK12_0 |UNUSED | |0 | | | | | | | | |
|A11 | |IOBS |IO_L39N_0 |UNUSED | |0 | | | | | | | | |
|A12 | |IOBS |IO_L41N_0 |UNUSED | |0 | | | | | | | | |
|A13 | |IOBS |IO_L50N_0 |UNUSED | |0 | | | | | | | | |
|A14 | |IOBS |IO_L62N_VREF_0 |UNUSED | |0 | | | | | | | | |
|A15 | |IOBS |IO_L64N_SCP4_0 |UNUSED | |0 | | | | | | | | |
|A16 | |IOBS |IO_L66N_SCP0_0 |UNUSED | |0 | | | | | | | | |
|A17 | | |TCK | | | | | | | | | | | |
|A18 | | |GND | | | | | | | | | | | |
|B1 | | |VCCAUX | | | | | | | |2.5 | | | |
|B2 |rx |IOB |IO_L2P_0 |INPUT |LVCMOS33 |0 | | | |NONE | |LOCATED |NO |NONE |
|B3 | |IOBM |IO_L4P_0 |UNUSED | |0 | | | | | | | | |
|B4 | |IOBM |IO_L5P_0 |UNUSED | |0 | | | | | | | | |
|B5 | | |VCCO_0 | | |0 | | | | |3.30 | | | |
|B6 | |IOBM |IO_L8P_0 |UNUSED | |0 | | | | | | | | |
|B7 | | |GND | | | | | | | | | | | |
|B8 | |IOBM |IO_L33P_0 |UNUSED | |0 | | | | | | | | |
|B9 | |IOBM |IO_L35P_GCLK17_0 |UNUSED | |0 | | | | | | | | |
|B10 | | |VCCO_0 | | |0 | | | | |3.30 | | | |
|B11 | |IOBM |IO_L39P_0 |UNUSED | |0 | | | | | | | | |
|B12 | |IOBM |IO_L41P_0 |UNUSED | |0 | | | | | | | | |
|B13 | | |GND | | | | | | | | | | | |
|B14 | |IOBM |IO_L62P_0 |UNUSED | |0 | | | | | | | | |
|B15 | | |VCCO_0 | | |0 | | | | |3.30 | | | |
|B16 | |IOBM |IO_L66P_SCP1_0 |UNUSED | |0 | | |
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XILINX FPGA SPARTAN6 UART串口通信实验 VERILOG逻辑例程源码 ISE14.7工程文件 module uart_test(clk50, rx, tx, reset); input clk50; input reset; input rx; output tx; wire clk; //clock for 9600 uart port wire [7:0] txdata,rxdata; wire idle; wire dataerror; wire frameerror; //产生时钟的频率为16*9600, clkdiv u0 ( .clk50 (clk50), .clkout (clk) ); uartrx u1 ( .clk (clk), .rx (rx)
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