AXI Quad SPI v3.1 www.xilinx.com 4
PG153 December 18, 2013 Product Specification
Introduction
The LogiCORE™ IP AXI Quad Serial Peripheral Interface
(SPI) core connects the AXI4 interface to those SPI slave
devices that support the Standard, Dual or Quad SPI
protocol instruction set. This core provides a serial
interface to SPI slave devices. The Dual/Quad SPI is an
enhancement to the Standard SPI protocol (described in
the Motorola M68HC11 data sheet) and provides a simple
method for data exchange between a master and a slave.
Features
• Configurable AXI4 interface; when configured with an
AXI4-Lite interface the core is backward compatible
with version 1.00 of the core (Legacy mode)
• Configurable AXI4 interface for burst mode operation
for Data Receive Register (DRR) and Data Transmit
Register (DTR) FIFO
• Configurable eXecute In Place (XIP) mode of
operation
• Connects as a 32-bit slave on either AXI4-Lite or AXI4
memory mapped interface
• Configurable SPI modes:
°
Standard SPI mode
°
Dual SPI mode
°
Quad SPI mode
• Standard SPI interfaces:
°
IO0 (MOSI) - Standard SPI mode
°
IO1 (MISO) - Standard SPI mode
°
SCK - Standard and Dual SPI mode
°
x SS - Standard and Dual SPI mode
• In Quad SPI mode supports six signal interfaces: IO0,
IO1, IO2, IO3, SCK and SS
• Up to 32 configurable SPI slaves
• Programmable SPI clock phase and polarity
• Configurable FIFO depth (16 or 256 element deep in
Dual/Quad/Standard SPI mode) and fixed FIFO depth
of 64 in XIP mode
IP Facts
LogiCORE IP Facts Table
Core Specifics
Supported
Device Family
(1)
UltraScale™ Architecture,
Zynq®-7000 All Programmable SoC,
7 Series FPGAs
Supported User
Interfaces
AXI4, AXI4-Lite
Resources See Ta bl e 2-3 through Table 2-5
Provided with Core
Design Files RTL
Example Design VHDL
Test B enc h VHDL
Constraints File XDC
Simulation
Model
Not Provided
Supported
S/W Driver
(2)
Standalone and Linux
Tested Design Flows
(3)
Design Entry
Vivado® Design Suite
Vivado IP integrator
Simulation
For a list of supported simulators, see the Xilinx
Design Tools: Release Notes Guide
Synthesis Vivado synthesis
Support
Provided by Xilinx @ www.xilinx.com/support
Notes:
1. For a complete list of supported devices, see Vivado IP
catalog.
2. Standalone driver details can be found in the SDK directory
(<install_directory>/doc/usenglish/xilinx_drivers.htm). Linux
OS and driver support information is available from
w
iki.xilinx.com.
3. For the supported versions of the tools, see the Xilinx Design
Tools: Release Notes Guide.
