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ADAU1787 data sheet
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ADAU1787是一款有双DSP(FastDSP和SigmaDSP)的codec,适用于做TWS耳机,或做音频的小伙伴。 ADAU1787 是一款具有四个输入和两个输出的编解码器,整合了两个数字信号处理器 (DSP)。从模拟输入到 DSP 内核再到模拟输出的路径已针对低延迟进行优化,适用于噪声消除耳机。通过加入少量无源组件,ADAU1787 提供了完整的耳机解决方案。
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Four ADC, Two DAC,
Low Power Codec with Audio DSPs
Data Sheet
ADAU1787
Rev. A Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2019-2020 Analog Devices, Inc. All rights reserved.
Technical Suppor t www.analog.com
FEATURES
Programmable FastDSP audio processing engine
Up to 768 kHz sample rate
Biquad filters, limiters, volume controls, mixing
28-bit SigmaDSP audio processing core
Visually programmable using SigmaStudio
Up to 50 MIPS performance
Low latency, 24-bit ADCs and DACs
96 dB SNR (signal through PGA and ADC with A-weighted
filter)
105 dB combined SNR (signal through DAC and headphone
with A-weighted filter)
Serial port f
SYNC
frequency from 8 kHz to 768 kHz
5 μs group delay (f
S
= 768 kHz) analog in to analog out with
FastDSP bypass (zero instructions)
4 single-ended analog inputs, configurable as microphone
or line inputs
8 digital microphone inputs
2 analog differential audio outputs, configurable as either
line output or headphone driver
PLL supporting any input clock rate from 30 kHz to 27 MHz
Full-duplex, 4-channel ASRCs
2, 16-channel serial audio ports supporting I
2
S, left justified,
or up to TDM16
8 interpolators and 8 decimators with flexible routing
Power supplies
Analog AVDD at 1.8 V typical
Digital I/O IOVDD at 1.1 V to 1.98 V
Digital DVDD at 0.9 V typical
Low power (11.079 mW for typical stereo ANC settings)
I
2
C and SPI control interfaces, self boot from I
2
C EEPROM
Flexible GPIO
42-ball, 0.35 mm pitch, 2.695 mm × 2.320 mm WLCSP
APPLICATIONS
Noise cancelling handsets, headsets, and headphones
Bluetooth ANC handsets, headsets, and headphones
Personal navigation devices
Digital still and video cameras
Musical instrument effect processors
Multimedia speaker systems
Smartphones
GENERAL DESCRIPTION
The ADAU1787 is a codec with four inputs and two outputs
that incorporates two digital signal processors (DSPs). The path
from the analog input to the DSP core to the analog output is
optimized for low latency and is ideal for noise cancelling
headsets. With the addition of just a few passive components,
the ADAU1787 provides a complete headset solution.
Note that throughout this data sheet, multifunction pins, such
as BCLK_0/MP1, are referred to either by the entire pin name
or by a single function of the pin, for example, BCLK_0, when
only that function is relevant.
ADAU1787 Data Sheet
Rev. A | Page 2 of 280
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Revision History ............................................................................... 5
Functional Block Diagram .............................................................. 6
Specifications ..................................................................................... 7
Analog Performance Specifications ........................................... 7
Crystal Amplifier Specifications ................................................. 9
Digital Input and Output Specifications ................................... 9
Power Supply Specifications...................................................... 10
Power-Down Current ................................................................ 10
Typical Power Consumption ..................................................... 10
Digital Filters ............................................................................... 11
Digital Timing Specifications ................................................... 12
Absolute Maximum Ratings .......................................................... 16
Thermal Resistance .................................................................... 16
ESD Caution ................................................................................ 16
Pin Configuration and Function Descriptions ........................... 17
Typical Performance Characteristics ........................................... 20
System Block Diagram ................................................................... 27
Theory of Operation ...................................................................... 28
System Clocking and Power-Up ................................................... 29
Power-Down Operation and Options ..................................... 29
Example ADC to DAC Power-up ............................................. 30
DVDD LDO Regulator .............................................................. 30
Clock Initialization ..................................................................... 30
PLL ............................................................................................... 31
Multichip Phase Synchronization ............................................ 32
Clock Output ............................................................................... 32
Power Supply Sequencing ......................................................... 32
Signal Routing ................................................................................. 33
Input Signal Paths ........................................................................... 34
Analog Inputs .............................................................................. 34
Digital Microphone Inputs ........................................................ 35
ADCs ............................................................................................ 36
Output Signal Paths ........................................................................ 37
Analog Outputs........................................................................... 37
DACs ............................................................................................ 37
PDM Outputs .............................................................................. 38
ASRCs .......................................................................................... 38
Interpolation and Decimation Blocks ..................................... 39
Signal Levels ................................................................................ 39
FastDSP Core .................................................................................. 40
Instructions ................................................................................. 40
Filter Precision ............................................................................ 40
Flags and Conditional Execution ............................................. 40
Input Sources .............................................................................. 40
Power and Run Control ............................................................. 41
Data Memory .............................................................................. 41
Parameters ................................................................................... 41
Parameter Bank Switching ........................................................ 41
Parameter Bank Copying .......................................................... 41
Parameter Memory Access........................................................ 42
FastDSP Parameter Safeload ..................................................... 42
SigmaDSP Core .............................................................................. 43
Read/Write Data Formats ......................................................... 44
Software Safeload ....................................................................... 45
FastDSP Safeload ........................................................................ 45
Program RAM, Parameter RAM, and Data RAM ..................... 46
Program RAM ............................................................................ 46
Parameter RAM .......................................................................... 46
Data RAM ................................................................................... 46
Power Saving Options .................................................................... 47
Control Port .................................................................................... 49
Burst Mode Communication .................................................... 49
Reading and Writing to Memories .......................................... 50
I
2
C Port ........................................................................................ 50
SPI Port ........................................................................................ 53
Self Boot ....................................................................................... 54
Multipurpose Pins ...................................................................... 56
Serial Data Ports ............................................................................. 57
Applications Information .............................................................. 59
Power Supply Bypass Capacitors .............................................. 59
Layout .......................................................................................... 59
Grounding ................................................................................... 59
PCB Stackup ................................................................................ 59
Register Summary .......................................................................... 60
Register Details ............................................................................... 67
ADI Vendor ID Register ............................................................ 67
Device ID Registers .................................................................... 67
Data Sheet ADAU1787
Rev. A | Page 3 of 280
Revision Code Register .............................................................. 67
ADC, DAC, Headphone Power Controls Register ................. 68
PLL, Microphone Bias, and PGA Power Controls Register .. 69
Digital Microphone Power Controls Register ......................... 70
Serial Port, PDM Output, and Digital Microphone CLK
Power Controls Register ............................................................. 71
DSP Power Controls Register .................................................... 72
ASRC Power Controls Register ................................................. 72
Interpolator Power Controls Register ...................................... 73
Decimator Power Controls Register ......................................... 74
State Retention Controls Register ............................................. 75
Chip Power Control Register ..................................................... 76
Clock Control Register ............................................................... 77
PLL Input Divider Register ........................................................ 78
PLL Feedback Integer Divider (LSBs Register) ....................... 78
PLL Feedback Integer Divider (MSBs Register) ..................... 78
PLL Fractional Numerator Value (LSBs Register) .................. 78
PLL Fractional Numerator Value (MSBs Register) ................ 79
PLL Fractional Denominator (LSBs Register) ......................... 79
PLL Fractional Denominator (MSBs Register) ....................... 79
PLL Update Register ................................................................... 79
ADC Sample Rate Control Register ......................................... 80
ADC I
BIAS
Controls Register ....................................................... 81
ADC HPF Control Register ....................................................... 81
ADC Mute and Compensation Control Register ................... 82
Analog Input Precharge Time Register .................................... 83
ADC Channel Mutes Register ................................................... 84
ADC Channel 0 Volume Control Register .............................. 85
ADC Channel 1 Volume Control Register .............................. 86
ADC Channel 2 Volume Control Register .............................. 87
ADC Channel 3 Volume Control Register .............................. 88
PGA Channel 0 Gain Control MSBs, Mute, Boost, Slew
Register ......................................................................................... 89
PGA Channel 0 Gain Control LSBs Register .......................... 89
PGA Channel 1 Gain Control MSBs, Mute, Boost, Slew
Register ......................................................................................... 90
PGA Channel 1 Gain Control LSBs Register .......................... 90
PGA Channel 2 Gain Control MSBs, Mute, Boost, Slew
Register ......................................................................................... 91
PGA Channel 2 Gain Control LSBs Register .......................... 91
PGA Channel 3 Gain Control MSBs, Mute, Boost, Slew
Register ......................................................................................... 92
PGA Channel 3 Gain Control LSBs Register .......................... 92
PGA Slew Rate and Gain Link Register ................................... 93
Microphone Bias Level and Current Register ......................... 93
Digital Microphone Clock Rate Control Register .................. 94
Digital Microphone Channel 0 and Channel 1 Rate, Order,
Mapping, and Edge Control Register .......................................... 95
Digital Microphone Channel 2 and Channel 3 Rate, Order,
Mapping, and Edge Control Register .......................................... 96
Digital Microphone Channel 4 and Channel 5 Rate, Order,
Mapping, and Edge Control Register .......................................... 97
Digital Microphone Channel 6 and Channel 7 Rate, Order,
Mapping, and Edge Control Register .......................................... 98
Digtial Microphone Volume Options Register ....................... 99
Digital Microphone Channel Mute Controls Register ......... 100
Digital Microphone Channel 0 Volume Control Register ... 101
Digital Microphone Channel 1 Volume Control Register ... 102
Digital Microphone Channel 2 Volume Control Register ... 103
Digital Microphone Channel 3 Volume Control Register ... 104
Digital Microphone Channel 4 Volume Control Register ... 105
Digital Microphone Channel 5 Volume Control Register ... 106
Digital Microphone Channel 6 Volume Control Register ... 107
Digital Microphone Channel 7 Volume Control Register ... 108
DAC Sample Rate, Filtering, and Power Controls Register ...... 109
DAC Volume Link, High-Pass Filter (HPF), and Mute
Controls Register ....................................................................... 110
DAC Channel 0 Volume Register ........................................... 111
DAC Channel 1 Volume Register ........................................... 112
DAC Channel 0 Routing Register ........................................... 113
DAC Channel 1 Routing Register ........................................... 115
Headphone Control Register ................................................... 117
Fast to Slow Decimator Sample Rates Channel 0 and Channel 1
Register ........................................................................................ 117
Fast to Slow Decimator Sample Rates Channel 2 and Channel 3
Register ........................................................................................ 118
Fast to Slow Decimator Sample Rates Channel 4 and Channel 5
Register ........................................................................................ 119
Fast to Slow Decimator Sample Rates Channel 6 and Channel 7
Register ........................................................................................ 120
Fast to Slow Decimator Channel 0 Input Routing Register ..... 121
Fast to Slow Decimator Channel 1 Input Routing Register ..... 122
Fast to Slow Decimator Channel 2 Input Routing Register ..... 124
Fast to Slow Decimator Channel 3 Input Routing Register ..... 125
Fast to Slow Decimator Channel 4 Input Routing Register ..... 127
ADAU1787 Data Sheet
Rev. A | Page 4 of 280
Fast to Slow Decimator Channel 5 Input Routing Register ..... 128
Fast to Slow Decimator Channel 6 Input Routing Register ..... 130
Fast to Slow Decimator Channel 7 Input Routing Register ..... 131
Slow to Fast Interpolator Sample Rates Channel 0 and
Channel 1 Register ................................................................... 133
Slow to Fast Interpolator Sample Rates Channel 2 and
Channel 3 Register ................................................................... 134
Slow to Fast Interpolator Sample Rates Channel 4 and
Channel 5 Register ................................................................... 135
Slow to Fast Interpolator Sample Rates Channel 6 and
Channel 7 Register ................................................................... 136
Slow to Fast Interpolator Channel 0 Input Routing Register
..................................................................................................... 137
Slow to Fast Interpolator Channel 1 Input Routing Register
..................................................................................................... 139
Slow to Fast Interpolator Channel 2 Input Routing Register
..................................................................................................... 141
Slow to Fast Interpolator Channel 3 Input Routing Register
..................................................................................................... 143
Slow to Fast Interpolator Channel 4 Input Routing Register
..................................................................................................... 145
Slow to Fast Interpolator Channel 5 Input Routing Register
..................................................................................................... 147
Slow to Fast Interpolator Channel 6 Input Routing Register
..................................................................................................... 149
Slow to Fast Interpolator Channel 7 Input Routing Register
..................................................................................................... 151
Input ASRC Control, Source, and Rate Selection Register . 153
Input ASRC Channel 0 and Channel 1 Input Routing Register
..................................................................................................... 154
Input ASRC Channel 2 and Channel 3 Input Routing Register
..................................................................................................... 155
Output ASRC Control Register .............................................. 156
Output ASRC Channel 0 Input Routing Register ................ 157
Output ASRC Channel 1 Input Routing Register ................ 158
Output ASRC Channel 2 Input Routing Register ................ 160
Output ASRC Channel 3 Input Routing Register ................ 161
FastDSP Run Register .............................................................. 163
FastDSP Current Bank and Bank Ramping Controls Register
..................................................................................................... 163
FastDSP Bank Ramping Stop Point Register ........................ 164
FastDSP Bank Copying Register ............................................ 165
FastDSP Frame Rate Source Register ..................................... 166
FastDSP Fixed Rate Division MSBs Register ........................ 166
FastDSP Fixed Rate Division LSBs Register ......................... 167
FastDSP Modulo N Counter for Lower Rate Conditional
Execution Register ................................................................... 167
FastDSP Generic Conditional Execution Registers ............. 168
FastDSP Safeload Address Register........................................ 169
FastDSP Safeload Parameter 0 Value Registers .................... 169
FastDSP Safeload Parameter 1 Value Registers .................... 170
FastDSP Safeload Parameter 2 Value Registers .................... 171
FastDSP Safeload Parameter 3 Value Registers .................... 172
FastDSP Safeload Parameter 4 Value Registers .................... 173
FastDSP Safeload Update Register ......................................... 174
SigmaDSP Frame Rate Source Select Register ..................... 174
SigmaDSP Run Register .......................................................... 175
SigmaDSP Watchdog Controls Register................................ 176
SigmaDSP Watchdog Value Registers ................................... 176
SigmaDSP Modulo Data Memory Start Position Registers 177
SigmaDSP Fixed Frame Rate Divisor Registers ................... 177
SigmaDSP Set Interrupts Register .......................................... 178
MultiPurpose Pin 0 and Pin 1 Mode Select Register ........... 179
MultiPurpose Pin 2 and Pin 3 Mode Select Register ........... 180
MultiPurpose Pin 4 and Pin 5 Mode Select Register ........... 181
MultiPurpose Pin 6 and Pin 7 Mode Select Register ........... 182
MultiPurpose Pin 8 and Pin 9 Mode Select Register ........... 183
MultiPurpose Pin 10 and Pin 11 Mode Select Register ...... 184
General-Purpose Input Debounce Control and Master Clock
Output Rate Selection Register ............................................... 185
General-Purpose Outputs Control Pin 0 to Pin 7 Register ..... 186
General-Purpose Outputs Control Pin 8 to Pin 10 Register ... 187
FSYNC_0 Pin Controls Register ............................................ 188
BCLK_0 Pin Controls Register ............................................... 189
SDATAO_0 Pin Control Register ........................................... 189
SDATAI_0 Pin Controls Register ........................................... 190
FSYNC_1 Pin Controls Register ............................................ 191
BCLK_1 Pin Controls Register ............................................... 192
SDATAO_1 Pin Controls Register ......................................... 193
SDATAI_1 Pin Controls Register ........................................... 194
DMIC_CLK0 Pin Controls Register ...................................... 195
DMIC_CLK1 Pin Controls Register ...................................... 196
DMIC01 Pin Controls Register .............................................. 197
DMIC23 Pin Controls Register .............................................. 198
SDA/MISO Pin Controls Register ......................................... 198
IRQ Signaling and Clearing Register ..................................... 199
IRQ1 Masking Registers .......................................................... 200
Data Sheet ADAU1787
Rev. A | Page 5 of 280
IRQ2 Masking Registers .......................................................... 203
Chip Resets Register ................................................................ 205
FastDSP Current Lambda Register ........................................ 206
Chip Status 1 Register .............................................................. 207
Chip Status 2 Register .............................................................. 208
General-Purpose Input Read 0 to Input Read 7 Register ... 209
General-Purpose Input Read 8 to Input Read 10 Register ...... 210
DSP Status Register .................................................................. 210
IRQ1 Status 1 Register ............................................................. 211
IRQ1 Status 2 Register ............................................................. 212
IRQ1 Status 3 Register ............................................................. 213
IRQ2 Status 1 Register ............................................................. 214
IRQ2 Status 2 Register ............................................................. 215
IRQ2 Status 3 Register ............................................................. 216
Serial Port 0 Control 1 Register .............................................. 217
Serial Port 0 Control 2 Register .............................................. 218
Serial Port 0 Output Routing Slot 0 (Left Register) ............. 219
Serial Port 0 Output Routing Slot 1 (Right Register) .......... 220
Serial Port 0 Output Routing Slot 2 Register ........................ 222
Serial Port 0 Output Routing Slot 3 Register ........................ 223
Serial Port 0 Output Routing Slot 4 Register ........................ 225
Serial Port 0 Output Routing Slot 5 Register ........................ 226
Serial Port 0 Output Routing Slot 6 Register ........................ 228
Serial Port 0 Output Routing Slot 7 Register ........................ 229
Serial Port 0 Output Routing Slot 8 Register ........................ 231
Serial Port 0 Output Routing Slot 9 Register ........................ 232
Serial Port 0 Output Routing Slot 10 Register ...................... 234
Serial Port 0 Output Routing Slot 11 Register ...................... 235
Serial Port 0 Output Routing Slot 12 Register ...................... 237
Serial Port 0 Output Routing Slot 13 Register ...................... 238
Serial Port 0 Output Routing Slot 14 Register ...................... 240
Serial Port 0 Output Routing Slot 15 Register ...................... 241
Serial Port 1 Control 1 Register .............................................. 243
Serial Port 1 Control 2 Register .............................................. 244
Serial Port 1 Output Routing Slot 0 (Left Register) .............. 245
Serial Port 1 Output Routing Slot 1 (Right Register) ........... 246
Serial Port 1 Output Routing Slot 2 Register ......................... 248
Serial Port 1 Output Routing Slot 3 Register ......................... 249
Serial Port 1 Output Routing Slot 4 Register ......................... 251
Serial Port 1 Output Routing Slot 5 Register ......................... 252
Serial Port 1 Output Routing Slot 6 Register ......................... 254
Serial Port 1 Output Routing Slot 7 Register ......................... 255
Serial Port 1 Output Routing Slot 8 Register ......................... 257
Serial Port 1 Output Routing Slot 9 Register ......................... 258
Serial Port 1 Output Routing Slot 10 Register ...................... 260
Serial Port 1 Output Routing Slot 11 Register ...................... 261
Serial Port 1 Output Routing Slot 12 Register ...................... 263
Serial Port 1 Output Routing Slot 13 Register ...................... 264
Serial Port 1 Output Routing Slot 14 Register ...................... 266
Serial Port 1 Output Routing Slot 15 Register ...................... 267
MP12 Pin Control Register...................................................... 269
SELFBOOT Pin Controls Register ......................................... 270
SW_EN Pin Controls Register ................................................ 271
PDM Sample Rate and Filtering Control Register ............... 272
PDM Muting, High-Pass, and Volume Options Register .... 273
PDM Output Channel 0 Volume Register ............................. 274
PDM Output Channel 1 Volume Register ............................. 275
PDM Output Channel 0 Routing Register ............................ 276
PDM Output Channel 1 Routing Register ............................ 278
Outline Dimensions ...................................................................... 280
Ordering Guide ......................................................................... 280
REVISION HISTORY
1/2020—Rev. 0 to Rev. A
Changes to Features Section ............................................................ 1
Changes to Typical Power Consumption Section
and Table 6 ....................................................................................... 10
Changes to Table 7 and Added Note 1 to Table 8 ....................... 11
Added Note 1 to Table 9, Renumbered Sequentially .................. 12
Changes to Figure 7 ......................................................................... 15
Changes to Table 10 ........................................................................ 16
Changes to Analog Input Precharge Time Register Section
and Table 67 .................................................................................... 83
4/2019—Revision 0: Initial Revision
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