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ADAU1452

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SigmaDSP Digital Audio Processor

Data Sheet

ADAU1452

Rev. A Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Technical Support www.analog.com

FEATURES

Qualified for automotive applications

Fully programmable audio DSP for enhanced sound

processing

Features SigmaStudio, a proprietary graphical programming

tool for the development of custom signal flows

294.912 MHz, 32-bit SigmaDSP core at 1.2 V

Up to 6144 SIMD instructions per sample at 48 kHz

40 kWords of parameter/data RAM

Up to 800 ms digital audio delay pool at 48 kHz

Audio I/O and routing

4 serial input ports, 4 serial output ports

48-channel, 32-bit digital I/O up to a sample rate of 192 kHz

Flexible configuration for TDM, I

S, left and right justified

formats, and PCM

Up to 8 stereo ASRCs from 1:8 up to 7.75:1 ratio and

139 dB DNR

Stereo S/PDIF input and output

Four PDM microphone input channels

Multichannel, byte addressable TDM serial ports

Clock oscillator for generating master clock from crystal

Integer PLL and flexible clock generators

Integrated die temperature sensor

C and SPI control interfaces (both slave and master)

Standalone operation

Self boot from serial EEPROM

6-channel, 10-bit SAR auxiliary control ADC

14 multipurpose pins for digital controls and outputs

On-chip regulator for generating 1.2 V from 3.3 V supply

72-lead, 10 mm × 10 mm LFCSP package with 5.3 mm

exposed pad

Temperature range: −40°C to +105°C

APPLICATIONS

Automotive audio processing

Head units

Navigation systems

Rear seat entertainment systems

DSP amplifiers (sound system amplifiers)

Commercial and professional audio processing

FUNCTIONAL BLOCK DIAGRAM

S/PDIF

TRANSMITTER

S/PDIF

RECEIVER

8 × 2-CHANNEL

ASYNCHRONOUS

SAMPLE RATE

CONVERTERS

INPUT

CLOCK

DOMAINS

(×4)

OUTPUT

CLOCK

DOMAINS

(×4)

CLOCK

OSCILLATOR

GPIO/

AUX ADC

PLL

C/SPI

SLAVE

XTALIN/MCLK

XTALOUT

SPI/I

BCLK_IN3 TO BCLK_IN0/

LRCLK_IN3 TO LRCLK_IN0

(INPUT CLOCK PAIRS)

SELFBOOT

SPDIFIN

SPDIFOUT

CLKOUT

SDATA_IN3 TO SDATA_IN0

(48-CHANNEL

DIGITAL AUDIO

INPUTS)

SDATA_OUT3 TO SDATA_OUT0

(48-CHANNEL

DIGITAL AUDIO

OUTPUTS)

REGULATOR

ADAU1452

PLLFILT

MP13 TO MP0

AUXADC5 TO

AUXADC0

BCLK_OUT3 TO BCLK_OUT0

LRCLK_OUT3 TO LRCLK_OUT0

(OUTPUT CLOCK PAIRS)

TEMPERATURE

SENSOR

THD_P

VDRIVE

THD_M

C/SPI

MASTER

SPI/I

DIGITAL

MIC INPUT

SERIAL DATA

INPUT PORTS

(×4)

SERIAL DATA

OUTPUT PORTS

(×4)

DEJITTER AND

CLOCK GENERATOR

*SPI/I

C INCLUDES THE FOLLOWING PIN FUNCTIONS: SS_M, MOSI_M, SCL_M, SCLK_M, SDA_M, MISO_M, MISO, SDA,

SCLK, SCL, MOSI, ADDR1, SS, AND ADDR0 PINS.

INPUT AUDIO

ROUTING MATRIX

OUTPUT AUDIO

ROUTING MATRIX

11486-001

294.912MHz

PROGRAMMABLE AUDIO

PROCESSING CORE

RAM, ROM, WATCHDOG,

MEMORY PARITY CHECK

Figure 1.

ADAU1452 Data Sheet

Rev. A | Page 2 of 176

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

General Description ......................................................................... 3

Specifications ..................................................................................... 4 

Electrical Characteristics ............................................................. 6

Timing Specifications .................................................................. 7

Absolute Maximum Ratings .......................................................... 15

Thermal Characteristics ............................................................ 15

Maximum Power Dissipation ................................................... 15

ESD Caution ................................................................................ 15

Pin Configuration and Function Descriptions ........................... 16

Theory of Operation ...................................................................... 20

System Block Diagram ............................................................... 20

Overvie w ...................................................................................... 20

Initialization ................................................................................ 22

Master Clock, PLL, and Clock Generators.............................. 25

Power Supplies, Voltage Regulator, and Hardware Reset ...... 29

Temperature Sensor Diode........................................................ 31

Slave Control Ports ..................................................................... 31

Master Control Ports .................................................................. 37

Self Boot ....................................................................................... 38

Audio Signal Routing ................................................................. 40

Serial Data Input/Output........................................................... 50

Flexible TDM Interface .............................................................. 60

Asynchronous Sample Rate Converters .................................. 65

S/PDIF Interface ......................................................................... 66

Digital PDM Microphone Interface ......................................... 68

Multipurpose Pins ...................................................................... 69

Auxiliary ADC ............................................................................ 72

SigmaDSP Core .......................................................................... 72

Software Features ....................................................................... 75

Pin Drive Strength, Slew Rate, and Pull Configuration ........ 77

Global RAM and Control Register Map ...................................... 78

Random Access Memory .......................................................... 78

Control Registers ........................................................................ 78

Control Register Details ................................................................ 89

PLL Configuration Registers .................................................... 89

Clock Generator Registers ........................................................ 93

Power Reduction Registers ....................................................... 97

Audio Signal Routing Registers .............................................. 100

Serial Port Configuration Registers ....................................... 106

Flexible TDM Interface Registers ........................................... 109

DSP Core Control Registers .................................................... 113

Debug and Reliability Registers .............................................. 118

DSP Program Execution Registers ......................................... 126

Multipurpose Pin Configuration Registers........................... 130

ASRC Status and Control Registers ....................................... 135

Auxiliary ADC Registers ......................................................... 138

S/PDIF Interface Registers ...................................................... 139

Hardware Interfacing Registers .............................................. 152

Soft Reset Register .................................................................... 170

Applications Information ............................................................ 171

PCB Design Considerations ................................................... 171

Typical Applications Block Diagram ..................................... 172

Example PCB Layout ............................................................... 173

PCB Manufacturing Guidelines ............................................. 174

Outline Dimensions ..................................................................... 175

Ordering Guide ........................................................................ 175

Automotive Products ............................................................... 175

REVISION HISTORY

1/14—Rev. 0 to Rev. A

Changed S/PDIF Transceiver and Receiver Maximum Audio

Sample Rate from 192 kHz to 96 kHz; Table 9 and Table 10 ...... 9

10/13—Revision 0: Initial Version

Data Sheet ADAU1452

Rev. A | Page 3 of 176

GENERAL DESCRIPTION

The ADAU1452 is an automotive-qualified audio processor that

far exceeds the digital signal processing capabilities of earlier

SigmaDSP® devices. Its restructured hardware architecture is

optimized for efficient audio processing. The audio processing

algorithms are realized in sample-by-sample and block- by-block

paradigms, which can both be executed simultaneously in a signal

processing flow created using the graphical programming tool,

SigmaStudio™. The new digital signal processor (DSP) core

architecture enables some types of audio processing algorithms

to be executed using significantly fewer instructions than were

required on previous SigmaDSP generations, leading to vastly

improved code efficiency.

The 1.2 V, 32-bit DSP core can run at frequencies of up to

294.912 MHz and execute up to 6144 instructions per sample at

the standard sample rate of 48 kHz. However, a wide range of

other sample rates are available, in addition to industry standard

rates. The integer PLL and flexible clock generator hardware can

generate up to 15 audio sample rates simultaneously. These clock

generators, along with the on-board asynchronous sample rate

converters (ASRCs) and flexible hardware audio routing matrix,

make the ADAU1452 an ideal audio hub that greatly simplifies

the design of complex multirate audio systems.

The ADAU1452 interfaces with a wide range of ADCs, DACs,

digital audio devices, amplifiers, and control circuitry, due to

its highly configurable serial ports, S/PDIF interfaces, and

multipurpose input/output pins. It can also directly interface

with PDM-output MEMS microphones, thanks to integrated

decimation filters specifically designed for that purpose.

Independent slave and master I

C/SPI control ports allow the

ADAU1452 not only to be programmed and configured by an

external master device, but also to program and configure external

slave devices directly. This, combined with self boot functionality,

enables the design of standalone systems that do not require any

external input to operate.

The power efficient DSP core executes full programs while

consuming only a few hundred milliwatts (mW) of power and

can run at a maximum program load while consuming less than

a watt, even in worst case temperatures exceeding 100°C. This

relatively low power consumption and small footprint make the

ADAU1452 an ideal replacement for large, general-purpose DSPs

that consume more power at the same processing load.

ADAU1452 Data Sheet

Rev. A | Page 4 of 176

SPECIFICATIONS

AVDD = 3.3 V ± 10%, DVDD = 1.2 V ± 5%, PVDD = 3.3 V ± 10%, IOVDD = 1.8 V – 10% to 3.3 V + 10%, T

= 25°C, master clock input =

12.288 MHz, core clock (f

CORE

) = 294.912 MHz, I/O pins set to low drive setting, unless otherwise noted.

Table 1.

Parameter Min Typ Max Unit Test Conditions/Comments

POWER

Supply Voltage

Analog Voltage (AVDD) 2.97 3.3 3.63 V Supply for analog circuitry, including auxiliary ADC

Digital Voltage (DVDD) 1.14 1.2 1.26 V

Supply for digital circuitry, including the DSP core, ASRCs, and signal

routing

PLL Voltage (PVDD) 2.97 3.3 3.63 V Supply for phase-locked loop (PLL) circuitry

I/O Supply Voltage (IOVDD) 1.71 3.3 3.63 V Supply for input/output circuitry, including pads and level shifters

Supply Current

Analog Current (AVDD) 1.5 1.73 2 mA

Idle State 0 5 40 μA Power applied, chip not programmed

Reset State 1.9 6.5 40 μA

Power applied, RESET

held low

PLL Current (PVDD) 9.5 10 13 mA 12.288 MHz MCLK with default PLL settings

Idle State 0 7.3 40 μA Power applied, PLL not configured

Reset State 3.9 8.5 40 μA

Power applied, RESET

held low

I/O Current (IOVDD)

Dependent on the number of active serial ports, clock pins, and

characteristics of external loads

Operation State 53 mA IOVDD = 3.3 V; all serial ports are clock masters

22 mA IOVDD = 1.8 V; all serial ports are clock masters

Power-Down State 0.3 2.5 mA IOVDD = 1.8 V – 10% to 3.3 V + 10%

Digital Current (DVDD)

Operation State

Maximum Program 350 415 mA

Typical Program 100 mA

Test program includes 16-channel I/O, 10-band EQ per channel,

all ASRCs active

Minimal Program 85 mA Test program includes 2-channel I/O, 10-band EQ per channel

Idle State 20 95 mA Power applied, DSP not enabled

Reset State 20 95 mA

Power applied, RESET

held low

ASYNCHRONOUS SAMPLE RATE

CONVERTERS

Dynamic Range 139 dB A-weighted, 20 Hz to 20 kHz

I/O Sample Rate 6 192 kHz

I/O Sample Rate Ratio 1:8 7.75:1

THD + N −120 dB

CRYSTAL OSCILLATOR

Transconductance 8.3 10.6 13.4 mS

REGULATOR

DVDD Voltage 1.14 1.2 V

Regulator maintains typical output voltage up to a maximum

800 mA load; IOVDD = 1.8 V – 10% to 3.3 V + 10%

Data Sheet ADAU1452

Rev. A | Page 5 of 176

AVDD = 3.3 V ± 10%, DVDD = 1.2 V ± 5%, PVDD = 3.3 V ± 10%, IOVDD = 1.8 V – 10% to 3.3 V + 10%, T

= −40°C to +105°C, master clock

input = 12.288 MHz, core clock (f

CORE

) = 294.912 MHz, I/O pins set to low drive setting, unless otherwise noted.

Table 2.

Parameter Min Typ Max Unit Test Conditions/Comments

POWER

Supply Voltage

Analog Voltage (AVDD) 2.97 3.3 3.63 V Supply for analog circuitry, including auxiliary ADC

Digital Voltage (DVDD) 1.14 1.2 1.26 V Supply for digital circuitry, including the DSP core, ASRCs, and signal routing

PLL Voltage (PVDD) 2.97 3.3 3.63 V Supply for PLL circuitry

IOVDD Voltage (IOVDD) 1.71 3.3 3.63 V Supply for input/output circuitry, including pads and level shifters

Supply Current

Analog Current (AVDD) 1.44 1.72 2 mA

Idle State 0 6.3 40 μA

Reset State 0.26 7.1 40 μA

PLL Current (PVDD) 6 10.9 15 mA 12.288 MHz master clock; default PLL settings

Idle State 0 7.8 40 μA Power applied, PLL not configured

Reset State 1.2 9.3 40 μA

Power applied, RESET

held low

I/O Current (IOVDD)

Dependent on the number of active serial ports, clock pins, and characteristics

of external loads

Operation State 47 mA IOVDD = 3.3 V; all serial ports are clock masters

15 mA IOVDD = 1.8 V; all serial ports are clock masters

Power-Down State 1.3 2.2 mA IOVDD = 1.8 V – 10% to 3.3 V + 10%

Digital Current (DVDD)

Operation State

Maximum Program 500 690 mA

Typical Program 200 mA Test program includes 16-channel I/O, 10-band EQ per channel, all ASRCs active

Minimal Program 160 mA Test program includes 2-channel I/O, 10-band EQ per channel

Idle State 315 635 mA

Reset State 315 635 mA

ASYNCHRONOUS SAMPLE

RATE CONVERTERS

Dynamic Range 139 dB A-weighted, 20 Hz to 20 kHz

I/O Sample Rate 6 192 kHz

I/O Sample Rate Ratio 1:8 7.75:1

THD + N −120 dB

CRYSTAL OSCILLATOR

Transconductance 8.1 10.6 14.6 mS

REGULATOR

DVDD Voltage 1.14 1.2 V

Regulator maintains typical output voltage up to a maximum 800 mA load;

IOVDD = 1.8 V – 10% to 3.3 V + 10%

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