【免费】【IC+/ICPLUS/九旸电子】IP175D数据手册资源-CSDN文库

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IP175DLF

Datasheet

1/140

May 23, 2011

5 Port 10/100 Ethernet Integrated Switch

(Policy-base QoS, Layer 2-4 MF Classifier, HW IGMP Snooping)

Features General Description



Wide operating temperature range

IP175DLF (0°C to 70°C)

IP175DLFI (-40°C to 85°C)



Built in 6 MAC and 5 PHY



Each port can be configured to be

10Based-T, 100Base-TX



Up to 2K MAC addresses



Support auto-polarity for 10Mbps



Broadcast storm protection



Auto MDI-MDIX



Support three MII/RMII ports



Layer2-4 Multi-Field classifier

Support 8-MultiField entry

Support traffic policy

Support Multi-Filed filter

Support copy to mirror port

Support trap to CPU port



Class of Service

Port based, MAC address, VID, VLAN

priority, IPv4 ToS, IPv6 DSCP,TCP/UDP

logical port and Multi-Field



QoS

Support policy-based QoS

Support 4-level priority queues per port

WRR/WFQ/SP



Support hardware IGMP v1,v2 snooping



Support Port mirror



Support 16 VLAN (IEEE Std 802.1q)

Port-based/tagged-based VLAN

Shared/Independent VLAN Learning

Support insert, remove tag

Support VLAN priority remarking



Support STP, RSTP and MSTP



Support port-based access control



Supports rate control(WFQ)

In/Out port rate control

Traffic Policy



Interrupt Pin



Support special tag and QinQ header



Support Link quality LED for 100Mbps



Support direct, serial and dual color LED



Built in Linear regulator control register



Support auto power saving mode



0.16um, 128-pin PQFP Lead Free package

IP175DLF integrates a 6-port switch

controller, SSRAM, and 5 10/100 Ethernet

transceivers. Each of the transceivers compliers

with the IEEE802.3, IEEE802.3u, and

IEEE802.3x specifications. The DSP approach is

utilized for designing transceivers with 0.16um

technology; they have high noise immunity and

robust performance.

IP175DLF operates in store and forward

mode. IP175DLF have a lot of rich feature for

different application, include router application,

firewall, IEEE 802.1Q, IGMP snooping,

policy-based QoS. It provides powerful QoS

function, include traffic policy, traffic meter, and

flexible queue scheduling (WRR/WFQ/SP). In

virtual LAN, IP175DLF support port-based VLAN

and IEEE 802.1Q tag-tagged VLAN (up to 16

VLAN groups).

IP175DLF support up to 2K MAC addresses,

up to 16 VLANs and up to 8 Multi-Field entries.

These tables are accessible through MII register.

The address table can configure either “2K

unicast addresses” or “1K unicast addresses and

1K multicast addresses“. The Multi-Field

classification is powerful classifier (layer2 to layer

4 packet headers) in packet classification. The

classifier divides incoming packets into multiple

classes based on prescribed rules. Each traffic

class from classifier can drop out-of-profile

packets, monitor traffic, specify forwarding

behavior, and specify output queue.

Beside a 5-port switch application, IP175DLF

supports three MII/RMII ports for router

application, one WAN port and one HOME/PNA

or Access point. The external MAC can monitor

or configure IP175DLF by accessing MII

registers through SMI0.

MII/RMII port also can be configured to be

MAC mode. It is used to interface an external

PHY to work as 5+1 switch. Through SMI1

IP175DLF can monitor and configure external

PHY.

IP175DLF

Datasheet

2/140

May 23, 2011

Table of Contents

Features............................................................................................................................................. 1

General Description............................................................................................................................ 1

Table of Contents ............................................................................................................................... 2

Revision History ................................................................................................................................. 5

Disclaimer .......................................................................................................................................... 5

Feature comparison between IP175C and IP175DLF ......................................................................... 6

Pin Diagram............................................................................................................................... 8

Pin Description......................................................................................................................... 12

Function Description ................................................................................................................ 36

3.1

Flow Control .................................................................................................................. 36

3.2

Broadcast Storm Protection ........................................................................................... 36

3.3

Rate Control .................................................................................................................. 36

3.4

External MII ................................................................................................................... 38

3.4.1

To define the speed, duplex and pause of MII port............................................. 39

3.4.2

The Application Circuit of RMII .......................................................................... 42

3.5

Virtual LAN (VLAN)........................................................................................................ 44

3.5.1

Port-based VLAN .............................................................................................. 44

3.5.2

Tag-based VLAN............................................................................................... 44

3.5.3

VLAN Ingress Filtering ...................................................................................... 44

3.5.4

Shared and Independent VLAN Learning .......................................................... 44

3.5.5

The determination of the requirement to insert or remove tag ............................ 44

3.6

Quality of Service (QoS) ................................................................................................ 45

3.6.1

Traffic Policy ..................................................................................................... 45

3.6.2

Priority Classification......................................................................................... 45

3.6.3

Output Queue Scheduling ................................................................................. 47

3.7

Port mirror ..................................................................................................................... 47

3.8

Layer 2-4 Multi-Field Classification ................................................................................ 47

3.9

MAC Address Table ....................................................................................................... 47

3.9.1

Entry Content.................................................................................................... 48

3.9.2

Accessing MAC Table ....................................................................................... 50

3.10

CPU Interrupt Control .................................................................................................... 51

3.11

IGMP Snooping ............................................................................................................. 51

3.12

Security Filtering............................................................................................................ 51

3.12.1

Physical Port Filtering ....................................................................................... 51

3.12.2

MAC Address Filtering ...................................................................................... 51

3.12.3

Logical Port Filtering ......................................................................................... 51

3.12.4

Layer 2-4 Multi-Field Filtering ............................................................................ 52

3.13

IEEE 802.1x .................................................................................................................. 52

3.14

Spanning Tree ............................................................................................................... 52

3.15

Special Tag.................................................................................................................... 52

3.16

Serial Mode LED ........................................................................................................... 54

3.17

LED Blink Timing ........................................................................................................... 56

3.18

Serial Management Interface ......................................................................................... 57

3.19

Reset ............................................................................................................................ 58

PHY Register ........................................................................................................................... 58

4.1

PHY ID Map .................................................................................................................. 58

4.2

PHY 0~4 Register Map .................................................................................................. 58

4.3

MII Register 0 of PHY0~4 .............................................................................................. 60

4.4

MII Register 1 of PHY0~4 .............................................................................................. 61

4.5

MII Register 2 of PHY0~4 (5 PHYs share the MII register) ............................................. 63

4.6

MII Register 3 of PHY0~4 (5 PHYs share the MII register) ............................................. 63

IP175DLF

Datasheet

3/140

May 23, 2011

4.7

MII Register 4 of PHY0~4 .............................................................................................. 64

4.8

MII Register 5 of PHY0~4 .............................................................................................. 66

4.9

MII Register 6 of PHY0~4 .............................................................................................. 67

4.10

MII Register 16 of PHY0~4 (5 PHYs share the MII register) ........................................... 67

4.11

MII Register 18 of PHY0~4 ............................................................................................ 67

4.12

MII Register 22 of PHY0~4 (5 PHYs share the MII register) ........................................... 68

Switch Register........................................................................................................................ 69

5.1

Switch Register Map...................................................................................................... 69

5.2

Switch Register EEPROM Map...................................................................................... 73

5.3

Switch Control Register ................................................................................................. 74

5.3.1

Chip Identification ............................................................................................. 74

5.3.2

Software Reset Register ................................................................................... 74

5.3.3

MII Force Mode................................................................................................. 75

5.3.4

Congestion Control Register ............................................................................. 75

5.3.5

Port State.......................................................................................................... 77

5.3.6

Illegal Frame Filter ............................................................................................ 77

5.3.7

Special Packet Identification.............................................................................. 78

5.3.7.1

Reserved Address 01-80-C2-00-00-00 to 01-80-C2-00-00-1F ...................78

5.3.8 80

5.3.8.1

Reserved Address 01-80-C2-00-00-20 to 01-80-C2-00-00-FF ...................81

5.3.8.2

Miscellaneous Special Packet Identification ..............................................81

5.3.9

Network Security............................................................................................... 84

5.3.10

Learning Control Register ................................................................................. 84

5.3.11

Aging Time Parameter ...................................................................................... 86

5.3.12

Broadcast Storm Protection............................................................................... 87

5.3.13

Port Mirror......................................................................................................... 88

5.3.14

Source Block Protection .................................................................................... 89

5.3.15

LED Control Register ........................................................................................ 90

5.4

External MII Control Register ......................................................................................... 91

5.4.1

External MII Status Report Register................................................................... 91

5.4.2

MII0 MAC Mode Register .................................................................................. 92

5.4.3

MII1 MAC Mode or MII2 MAC Mode Register .................................................... 93

5.4.4

MII0, MII1 and MII2 Control Register 1 .............................................................. 94

5.4.5

MII0, MII1 and MII2 Control Register 2 .............................................................. 96

5.5

IGMP Control Register................................................................................................... 96

5.5.1

Base Control Register ....................................................................................... 96

5.5.2

Router Port Timeout .......................................................................................... 97

5.5.3

IGMP Group Timeout ........................................................................................ 98

5.6

Rate Control .................................................................................................................. 99

5.6.1

Basic Rate Setting Register............................................................................... 99

5.6.2

Rate Setting Access Control Register ................................................................ 99

5.7

Address Table Access Register.................................................................................... 100

5.7.1

Command Register ......................................................................................... 100

5.7.2

Data Buffer Register (For Unicast MAC Address) ............................................ 100

5.7.3

Data Buffer Register (For Multicast MAC Address) .......................................... 100

5.7.4

Data Buffer Register (For IP Multicast Address)............................................... 101

5.8

CPU Interrupt Register ................................................................................................ 102

5.8.1

CPU Interrupt Control Register........................................................................ 102

5.8.2

CPU Interrupt Enable Register ........................................................................ 102

5.8.3

CPU Interrupt Status Register ......................................................................... 102

5.9

Miscellaneous Control Register ................................................................................... 103

5.10

CRC Counter............................................................................................................... 105

5.11

VLAN Group Control Register...................................................................................... 105

5.11.1

VLAN Classification......................................................................................... 105

IP175DLF

Datasheet

4/140

May 23, 2011

5.11.2

VLAN Ingress Rule ......................................................................................... 107

5.11.3

VLAN Egress Rule .......................................................................................... 107

5.11.4

Default VLAN Information................................................................................ 108

5.11.5

VLAN Table..................................................................................................... 109

5.11.5.1

VLAN Control Register............................................................................109

5.11.5.2

VLAN Identifier Register .........................................................................109

5.11.5.3

VLAN Member Register .......................................................................... 110

5.11.5.4

Add Tag Control Register ........................................................................112

5.11.5.5

Remove Tag Control Register .................................................................113

5.11.5.6

VLAN Miscellaneous Register.................................................................115

5.11.5.7

Spanning Tree Table ...............................................................................116

5.12

Quality of Service (QOS) ..............................................................................................117

5.12.1

Priority Classification........................................................................................117

5.12.1.1

Base Control Register.............................................................................117

5.12.1.2

Port Priority Map.....................................................................................117

5.12.1.3

VLAN Priority Map ..................................................................................118

5.12.1.4

TOS/DSCP Priority Map.......................................................................... 119

5.12.1.5

TCP/UDP Port Priority ............................................................................122

5.12.2

Queue Scheduling Configuration Register....................................................... 123

5.13

QoS Multi-Field Classification ...................................................................................... 125

5.13.1

Multi-Field Classification Table Control Register .............................................. 125

5.13.2

Multi-Field Classification Register.................................................................... 126

5.13.3

Multi-Field Table QoS Rate Control Register.................................................... 128

5.13.4

Multi-Field Access Control Register ................................................................. 128

5.13.5

Multi-Field Status Register............................................................................... 129

Crystal Specifications............................................................................................................. 130

Electrical Characteristics........................................................................................................ 131

7.1

Absolute Maximum Rating ........................................................................................... 131

7.2

DC Characteristic ........................................................................................................ 131

7.3

AC Timing.................................................................................................................... 132

7.3.1

Power On Sequence and Reset Timing ........................................................... 132

7.3.2

PHY Mode MII (Turbo MII) Timing ................................................................... 133

7.3.3

MAC Mode MII (Turbo MII) Timing................................................................... 134

7.3.4

RMII Timing .................................................................................................... 135

7.3.5

SNI Timing ...................................................................................................... 136

7.3.6

SMI Timing...................................................................................................... 137

7.3.7

EEPROM Timing............................................................................................. 139

7.4

Thermal Data............................................................................................................... 139

Order Information................................................................................................................... 139

Package Detail....................................................................................................................... 140

剩余139页未读，继续阅读

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