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【IC+/ICPLUS/九旸电子】IP804A数据手册
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【IC+/ICPLUS/九旸电子】IP804A数据手册
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IP804A
Preliminary Datasheet
1 / 47 May 2, 2017
Copyright © 2017, IC Plus Corp. IP804A-DS-R01
4-Port PSE Controller for PoE Systems
Features General Description
IEEE 802.3AF-2003 and 802.3AT-2009
compliant
Single DC power supply voltage input (45~57V)
Wide temperature range: -40℃~+85℃
Supplies 4 independent power ports
Built-in power FETs
I
2
C Bus to access up to 8 x IP804A devices
Continuous system monitoring for every port
Independent system parameters setting for
every port
Thermal monitoring and protection
Built-in 3.3V regulators for external devices
Built-in Power on Reset
Configurations: (1) 30W x 4 ports
Total Current Limit
Built-in LEDs control
Built-in EEPROM interface for dumb application
Package and operation temperature
48 Pin(7mmx7mm) MQFN, -40~85
℃
Application
4 port PSE Switch
8 port PSE Switch
IP804A is an 4-port PSE (Power Sourcing
Equipment) controller IC for PoE (Power over
Ethernet) systems. It integrates power, analog and
logic circuits into a single chip, and can be used for
Midcap and Endpoint PSE applications.
IP804A meets all IEEE 802.3AF-2003
requirements, such as multi-point resistor
detection, PD classification, DC Disconnect, and
Back-off for Midcap. It also meets all IEEE
802.3AT-2009 requirements, such as two-event
classification and supply maximum 36W per port.
IP804A comprises internal temperature
monitoring and thermal protection to protect
against junction overheating. The 3.3V regulator
is built-in to support external devices. Multiple
IP804As can integrate to build an 4 x N ports PSE
system, and I
2
C bus uses to collect PD power
status from each IP804A to support global power
managements.
Multiple IP804As can build a cost effective PHY
level PSE system to support PD classification and
power management without a host. With a
management host, a networked LLDP (Link Layer
Discovery Protocol) based multiple IP804As PSE
system can be built. Based on LLDP (part of IEEE
Std 802.3AT-2009), dynamic power management
between PSE and PD can be maintained in real
time for power efficiency.
Management switch host has options to
communicate IP804As via I
2
C bus for PSE
management activities. Opt couplers can be
implemented to provide electrical isolations
between the host and IP804As for signal
communication.
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IP804A
Preliminary Datasheet
2 / 47 May 2, 2017
Copyright © 2017, IC Plus Corp. IP804A-DS-R01
Table of Contents
Features ................................................................................................................................................................................. 1
General Description .............................................................................................................................................................. 1
Table of Contents .................................................................................................................................................................. 2
List of Figures ........................................................................................................................................................................ 3
List of Tables .......................................................................................................................................................................... 3
Revision History ..................................................................................................................................................................... 4
1 Pin diagram ..................................................................................................................................................................... 5
1.1 IP804A Pin diagram (MQFN48) ................................................................................................ 5
2 IP804A application diagram .......................................................................................................................................... 6
2.1 Dumb & Smart device application ............................................................................................. 6
3 Block diagram ................................................................................................................................................................. 7
3.1 Blocks Description ..................................................................................................................... 8
3.1.1 Global Blocks ................................................................................................................. 9
3.1.2 Per Port Block .............................................................................................................. 10
4 Pin description ............................................................................................................................................................... 11
5 Functional Description .................................................................................................................................................. 13
5.1 System Reset .......................................................................................................................... 13
5.2 Operation Modes & System Configuration ............................................................................. 14
5.3 I
2
C Slave Interface .................................................................................................................. 16
5.4 EEPROM controller ................................................................................................................. 18
5.5 PSE State Machine ................................................................................................................. 19
5.6 Power Manager ....................................................................................................................... 22
5.6.1 Power Trunks ............................................................................................................... 22
5.6.2 Power Configuration .................................................................................................... 22
5.6.3 Port Polling ................................................................................................................... 25
5.6.4 Power Event Handling ................................................................................................. 26
5.7 Real time Monitor Power Event .............................................................................................. 27
5.8 Port Status and Interrupt ......................................................................................................... 28
5.9 Total Current Limit ................................................................................................................... 30
5.10 LED Interface .......................................................................................................................... 31
6 IP804A Register descriptions ...................................................................................................................................... 34
7 Electrical Characteristics .............................................................................................................................................. 38
7.1 Absolute Maximum Ratings .................................................................................................... 38
7.2 Operating Conditions .............................................................................................................. 38
7.3 Electrical Characteristics for Analog I/O Pins ......................................................................... 38
7.4 IEEE802.3 AF/AT Mode Parameters ...................................................................................... 39
7.5 Digital Electrical Characteristics .............................................................................................. 42
7.6 AC Timing ................................................................................................................................ 43
7.6.1 Power On Sequence and Reset Timing ...................................................................... 43
7.6.2 EEPROM Timing .......................................................................................................... 44
7.6.2.1 Data read cycle .................................................................................................. 44
7.6.2.2 Command cycle ................................................................................................. 44
7.6.3 I
2
C Timing .................................................................................................................... 45
7.6.3.1 Data read cycle .................................................................................................. 45
7.6.3.2 Command cycle ................................................................................................. 45
7.7 Thermal Data ........................................................................................................................... 45
8 Order Information .......................................................................................................................................................... 46
9 Package Detail .............................................................................................................................................................. 47
9.1 48 MQFN Outline Dimensions (in mm) ................................................................................... 47
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IP804A
Preliminary Datasheet
3 / 47 May 2, 2017
Copyright © 2017, IC Plus Corp. IP804A-DS-R01
List of Figures
Figure 1 Pin Diagram ............................................................................................................... 5
Figure 2 Application Diagram .................................................................................................. 6
Figure 3 Block Diagram ........................................................................................................... 7
Figure 4 I
2
C bus read/write cycles diagram ........................................................................... 16
Figure 5 EEPROM Format ..................................................................................................... 18
Figure 6 LED behavior and system diagram of multiple IP804A application ........................ 33
Figure 7 Typical Power up Sequence .................................................................................... 40
Figure 8 Power on Sequence and Reset Timing Diagram .................................................... 43
Figure 9 EEPROM Read Cycle Timing Diagram ................................................................... 44
Figure 10 EEPROM Command Cycle Timing Diagram........................................................... 44
Figure 11 I
2
C Read Cycle Timing Diagram .............................................................................. 45
Figure 12 I
2
C Command Cycle Timing Diagram ..................................................................... 45
Figure 13 Package Outline Dimensions .................................................................................. 47
List of Tables
Table 1 Pin description ............................................................................................................. 11
Table 2 Mode Setting ............................................................................................................... 15
Table 3 Available functions in Operation modes ...................................................................... 15
Table 4 Port power off conditions ............................................................................................. 27
Table 5 Register Page 0 description ........................................................................................ 34
Table 6 Register Page 1 description ........................................................................................ 36
Table 7 Electrical Characteristics ............................................................................................. 38
Table 8 IEEE802.3 AF/AT Mode Parameters ........................................................................... 39
Table 9 Digital Electrical Characteristics .................................................................................. 42
Table 10 Order Information ...................................................................................................... 46
![](https://csdnimg.cn/release/download_crawler_static/88958085/bg4.jpg)
IP804A
Preliminary Datasheet
4 / 47 May 2, 2017
Copyright © 2017, IC Plus Corp. IP804A-DS-R01
Revision History
Revision # Date Change Description
IP804A-DS-R01
2017/05/02 Initial release
![](https://csdnimg.cn/release/download_crawler_static/88958085/bg5.jpg)
IP804A
Preliminary Datasheet
5 / 47 May 2, 2017
Copyright © 2017, IC Plus Corp. IP804A-DS-R01
SCAN0
SCAN1
VRext
RGND
V54
AGND
V5
V3P3
V2P5
VPP
In_Top
EnB_Reg
1 Pin diagram
1.1 IP804A Pin diagram (MQFN48)
(7mm X 7mm Top view)
Exposed pad is system GND, must be soldered to PCB ground plane
Figure 1 Pin Diagram
PortN3
AGND
RS3
AGND
13
14
15
16
17
18
19
20
21
22
23
24
10
11
12
27
26
25
LED_CLK
AGND
AGND
AGND
RS0
PortN0
RS1
PortN1
AGND
RS2
PortN2
1
2
3
4
5
6
7
8
9
36
35
34
33
32
31
30
29
28
48
47
46
45
44
43
42
41
40
39
38
37
Exposed PAD
(Ground)
AD0
AD1
AD2
RstN
DV3P3
DGND
INITB
SDAI/EE_DAT
SDAO
SCL/EE_CLK
LED_DAT
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
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