IP175D-DS-R02-20071004.pdf_IP175D资源-CSDN文库

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IP175D

Preliminary Datasheet

1/135

October 4, 2007

5 Port 10/100 Ethernet Integrated Switch

(Policy-base QoS, Layer 2-4 MF Classifier, HW IGMP Snooping)

Features General Description

z Built in 6 MAC and 5 PHY

z Each port can be configured to be

10Based-T, 100Base-TX

z Up to 2K MAC addresses

z Support auto-polarity for 10Mbps

z Broadcast storm protection

z Auto MDI-MDIX

z Support three MII/RMII ports

z Layer2-4 Multi-Field classifier

- Support 8-MultiField entry

- Support traffic policy

- Support Multi-Filed filter

- Support copy to mirror port

- Support trap to CPU port

z Class of Service

- Port based, MAC address, VID, VLAN

priority, IPv4 ToS, IPv6 DSCP,TCP/UDP

logical port and Multi-Field

z QoS

- Support policy-based QoS

- Support 4-level priority queues per port

- WRR/WFQ/SP

z Support hardware IGMP v1,v2 snooping

z Support Port mirror

z Support 16 VLAN (IEEE Std 802.1q)

- Port-based/tagged-based VLAN

- Shared VLAN Learning/Independent

VLAN Learning (SVL/IVL)

- Support insert, remove tag

- Support VLAN priority remarking

z Support STP, RSTP and MSTP

z Support port-based access control

z Supports rate control

- In/Out port rate control

- Traffic Policy

- WFQ

z Interrupt Pin

z Support special tag

z Support double tag header

z Support Link quality LED for 100Mbps

z Support direct, serial and dual color LED

z Built in Linear regulator control register

z Low power consumption

z 0.16um, 128-pin PQFP

IP175D integrates a 6-port switch controller,

SSRAM, and 5 10/100 Ethernet transceivers.

Each of the transceivers compliers with the

IEEE802.3, IEEE802.3u, and IEEE802.3x

specifications. The DSP approach is utilized for

designing transceivers with 0.16um technology;

they have high noise immunity and robust

performance.

IP175D operates in store and forward mode.

IP175D have a lot of rich feature for different

application, include router application, firewall,

IEEE 802.1Q, IGMP snooping, policy-based

QoS. It provides powerful QoS function, include

traffic policy, traffic meter, and flexible queue

scheduling (WRR/WFQ/SP). In virtual LAN,

IP175D support port-based VLAN and IEEE

802.1Q tag-tagged VLAN (up to 16 VLAN

groups).

IP175D support up to 2K MAC addresses, up

to 16 VLANs and up to 8 Multi-Field entries.

These tables are accessible through MII register.

The address table can configure either “2K

unicast addresses” or “1K unicast addresses and

1K multicast addresses“. The Multi-Field

classification is powerful classifier (layer2 to layer

4 packet headers) in packet classification. The

classifier divides incoming packets into multiple

classes based on prescribed rules. Each traffic

class from classifier can drop out-of-profile

packets, monitor traffic, specify forwarding

behavior, and specify output queue.

Beside a 5-port switch application, IP175D

supports three MII/RMII ports for router

application, one WAN port and one HOME/PNA

or Access point. The external MAC can monitor

or configure IP175D by accessing MII registers

through SMI0.

MII/RMII port also can be configured to be

MAC mode. It is used to interface an external

PHY to work as 5+1 switch. Through SMI1

IP175D can monitor and configure external

PHY..

IP175D

Preliminary Datasheet

3/135

October 4, 2007

Table of Contents

Features................................................................................................................................................... 1

General Description ................................................................................................................................. 1

Table of Contents..................................................................................................................................... 3

Revision

y....................................................................................................................................... 6

Feature comparison between IP175C and IP175D................................................................................. 7

Pin Diagram .................................................................................................................................... 9

2 Pin Description.............................................................................................................................. 13

3 Function Description ..................................................................................................................... 36

3.1

Flow Control ....................................................................................................................... 36

3.2 Broadcast Storm Protection ............................................................................................... 36

3.3 Rate Control ....................................................................................................................... 36

3.4

External MII ........................................................................................................................ 38

3.4.1 To define the speed, duplex and pause of MII port............................................... 39

3.4.2 The Application Circuit of RMII.............................................................................. 42

3.5

Virtual LAN (VLAN) ............................................................................................................ 44

3.5.1 Port-based VLAN .................................................................................................. 44

3.5.2 Tag-based VLAN................................................................................................... 44

3.5.3

VLAN Ingress Filtering .......................................................................................... 44

3.5.4 Shared and Independent VLAN Learning............................................................. 44

3.5.5 The determination of the requirement to insert or remove tag.............................. 44

3.6

Quality of Service (QoS) .................................................................................................... 45

3.6.1 Traffic Policy.......................................................................................................... 45

3.6.2 Priority Classification............................................................................................. 45

3.6.3

Output Queue Scheduling..................................................................................... 47

3.7 Port mirror .......................................................................................................................... 47

3.8 Layer 2-4 Multi-Field Classification .................................................................................... 47

3.9

MAC Address Table............................................................................................................ 47

3.9.1 Entry Content ........................................................................................................ 48

3.9.2

Accessing MAC Table ........................................................................................... 50

3.10 CPU Interrupt Control......................................................................................................... 51

3.11 IGMP Snooping.................................................................................................................. 51

3.12

Security Filtering................................................................................................................. 51

3.12.1

Physical Port Filtering ........................................................................................... 51

3.12.2 MAC Address Filtering .......................................................................................... 52

3.12.3

Logical Port Filtering ............................................................................................. 52

3.12.4

Layer 2-4 Multi-Field Filtering................................................................................ 52

3.13 IEEE 802.1x ....................................................................................................................... 52

3.14

Spanning Tree .................................................................................................................... 52

3.15 Special Tag......................................................................................................................... 53

3.16 Serial Mode LED ................................................................................................................ 54

3.17

LED Blink Timing................................................................................................................56

3.18

Serial Management Interface............................................................................................. 57

3.19 Reset .................................................................................................................................. 58

PHY Register ................................................................................................................................ 58

4.1

PHY Register Map.............................................................................................................. 58

4.2

MII Register 0 of PHY0~4 .................................................................................................. 59

4.3

MII Register 1 of PHY0~4 .................................................................................................. 60

4.4

MII Register 2 of PHY0~4 (5 PHYs share the MII register) ............................................... 62

4.5

MII Register 3 of PHY0~4 (5 PHYs share the MII register) ............................................... 62

4.6 MII Register 4 of PHY0~4 .................................................................................................. 63

4.7

MII Register 5 of PHY0~4 .................................................................................................. 65

4.8

MII Register 6 of PHY0~4 .................................................................................................. 66

IP175D

Preliminary Datasheet

4/135

October 4, 2007

Switch Register ............................................................................................................................. 67

5.1 Switch Register Map .......................................................................................................... 67

5.2

Switch Control Register...................................................................................................... 71

5.2.1

Software Reset Register ....................................................................................... 71

5.2.2 MII Force Mode ..................................................................................................... 72

5.2.3 Congestion Control Register................................................................................. 72

5.2.4

Port State............................................................................................................... 74

5.2.5 Illegal Frame Filter ................................................................................................ 74

5.2.6

Special Packet Identification ................................................................................. 75

5.2.6.1 Reserved Address 01-80-C2-00-00-00 to 01-80-C2-00-00-1F ................... 75

5.2.7 77

5.2.7.1 Reserved Address 01-80-C2-00-00-20 to 01-80-C2-00-00-FF................... 78

5.2.7.2 Miscellaneous Special Packet Identification................................................ 78

5.2.8 Network Security ................................................................................................... 81

5.2.9

Learning Control Register ..................................................................................... 81

5.2.10 Aging Time Parameter .......................................................................................... 83

5.2.11 Broadcast Storm Protection .................................................................................. 84

5.2.12

Port Mirror ............................................................................................................. 85

5.2.13 Source Block Protection........................................................................................ 86

5.2.14 LED Control Register ............................................................................................ 87

5.3

External MII Control Register............................................................................................. 88

5.3.1 External MII Status Report Register...................................................................... 88

5.3.2 MII0 MAC Mode Register...................................................................................... 89

5.3.3

MII1 MAC Mode or MII2 MAC Mode Register ...................................................... 90

5.3.4 MII0, MII1 and MII2 Control Register 1 ................................................................. 91

5.3.5 MII0, MII1 and MII2 Control Register 2 ................................................................. 93

5.4

IGMP Control Register ....................................................................................................... 93

5.4.1 Base Control Register........................................................................................... 93

5.4.2

Router Port Timeout.............................................................................................. 94

5.4.3 IGMP Group Timeout ............................................................................................ 95

5.5 Rate Control ....................................................................................................................... 96

5.5.1

Basic Rate Setting Register .................................................................................. 96

5.5.2 Rate Setting Access Control Register................................................................... 96

5.6 Address Table Access Register.......................................................................................... 97

5.6.1

Command Register ............................................................................................... 97

5.6.2 Data Buffer Register (For Unicast MAC Address)................................................. 97

5.6.3

Data Buffer Register (For Multicast MAC Address) .............................................. 97

5.6.4

Data Buffer Register (For IP Multicast Address) ................................................... 98

5.7

CPU Interrupt Register....................................................................................................... 99

5.7.1

CPU Interrupt Control Register ............................................................................. 99

5.7.2

CPU Interrupt Enable Register.............................................................................. 99

5.7.3

CPU Interrupt Status Register............................................................................... 99

5.8

Miscellaneous Control Register ....................................................................................... 100

5.9

CRC Counter.................................................................................................................... 102

5.10

VLAN Group Control Register.......................................................................................... 102

5.10.1

VLAN Classification............................................................................................. 102

5.10.2

VLAN Ingress Rule.............................................................................................. 103

5.10.3

VLAN Egress Rule .............................................................................................. 103

5.10.4

Default VLAN Information ................................................................................... 104

5.10.5

VLAN Table ......................................................................................................... 105

5.10.5.1 VLAN Control Register.............................................................................. 105

5.10.5.2

VLAN Identifier Register............................................................................ 105

5.10.5.3

VALN Member Register............................................................................. 106

5.10.5.4 Add Tag Control Register .......................................................................... 108

IP175D

Preliminary Datasheet

5/135

October 4, 2007

5.10.5.5

Remove Tag Control Register ................................................................... 109

5.10.5.6 VLAN Miscellaneous Register....................................................................111

5.10.5.7

Spanning Tree Table...................................................................................112

5.11

Quality of Service (QOS).................................................................................................. 113

5.11.1 Priority Classification........................................................................................... 113

5.11.1.1 Base Control Register ................................................................................113

5.11.1.2

Port Priority Map.........................................................................................113

5.11.1.3 VLAN Priority Map......................................................................................114

5.11.1.4

TOS/DSCP Priority Map.............................................................................115

5.11.1.5 TCP/UDP Port Priority................................................................................118

5.11.2 Queue Scheduling Configuration Register.......................................................... 119

5.12

QoS Multi-Field Classification .......................................................................................... 121

5.12.1 Multi-Field Classification Table Control Register................................................. 121

5.12.2 Multi-Field Classification Register....................................................................... 122

5.12.3

Multi-Field Table QoS Rate Control Register...................................................... 124

5.12.4 Multi-Field Access Control Register.................................................................... 124

5.12.5 Multi-Field Status Register .................................................................................. 125

Electrical Characteristics............................................................................................................. 126

6.1 Absolute Maximum Rating ............................................................................................... 126

6.2 DC Characteristic ............................................................................................................. 126

6.3

AC Timing......................................................................................................................... 127

6.3.1 Reset Timing ....................................................................................................... 127

6.3.2 PHY Mode MII Timing ......................................................................................... 127

6.3.3

MAC Mode MII Timing......................................................................................... 129

6.3.4 RMII Timing ......................................................................................................... 130

6.3.5 SNI Timing........................................................................................................... 131

6.3.6

SMI Timing .......................................................................................................... 132

6.3.7 EEPROM Timing................................................................................................. 134

6.4

Thermal Data.................................................................................................................... 134

7 Order Information........................................................................................................................ 134

8 Package Detail............................................................................................................................ 135

剩余134页未读，继续阅读

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