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AXI Video Direct Memory Access v6.2 LogiCORE IP Product Guide--VIVADO官方IP核AXI DMA数据手册
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AXI Video Direct
Memory Access v6.2
LogiCORE IP Product Guide
Vivado Design Suite
PG020 November 30, 2016
AXI VDMA v6.2 2
PG020 November 30, 2016
www.xilinx.com
Table of Contents
IP Facts
Chapter 1: Overview
Feature Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Unsupported Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Licensing and Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Chapter 2: Product Specification
Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Resource Utilization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Port Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Register Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Genlock Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Chapter 3: Designing with the Core
General Design Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Clocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Programming Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Chapter 4: Design Flow Steps
Customizing and Generating the Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Constraining the Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Synthesis and Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Chapter 5: Example Design
Implementing the Example Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Test Bench for the Example Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Simulating the Example Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
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AXI VDMA v6.2 3
PG020 November 30, 2016
www.xilinx.com
Chapter 6: General Use Cases
Appendix A: Migrating and Updating
Migrating to the Vivado Design Suite. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Upgrading in the Vivado Design Suite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Appendix B: Debugging
Finding Help on Xilinx.com . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Vivado Design Suite Debug Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Hardware Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Appendix C: Frame Pointers Gray Code Outputs
Appendix D: Additional Resources and Legal Notices
Xilinx Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Please Read: Important Legal Notices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
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AXI VDMA v6.2 4
PG020 November 30, 2016
www.xilinx.com Product Specification
Introduction
The Xilinx® LogiCORE™ IP AXI VDMA core is a
soft IP core. It provides high-bandwidth direct
memory access between memory and
AXI4-Stream video type target peripherals
including peripherals which support the
AXI4-Stream Video protocol as described in the
Video IP: AXI Feature Adoption section of the
Vivado AXI Reference Guide (UG1037)
[Ref 1].
Features
• AXI4 Compliant
• Primary AXI4 data width support of 32, 64,
128, 256, 512, and 1,024 bits
• Primary AXI4-Stream data width support of
multiples of 8 up to 1,024 bits
• Optional Data Re-Alignment Engine
• Optional Genlock Synchronization
• Independent, asynchronous channel
operation
• Dynamic clock frequency change of
AXI4-Stream interface clocks
• Optional frame advance or repeat on error
• Supports up to 32 frame buffers
• Supports up to 64-bit address space
IP Facts
LogiCORE IP Facts Table
Core Specifics
Supported
Device
Family
(1)
UltraScale+™
UltraScale™
Zynq®-7000, 7 Series
Supported
User Interfaces
AXI4, AXI4-Lite, AXI4-Stream
Resources See Table 2-4 and Table 2-5
Provided with Core
Design Files
(2)
VHDL
Example
Design
Provided
Test Bench Provided
Constraints
File
Provided
Simulation
Model
Not Provided
Supported
S/W Drivers
(3)
Standalone and Linux
Tested Design Flows
(4)
Design Entry Vivado® Design Suite
Simulation
For supported simulators, see the
Xilinx Design Tools: Release Notes Guide
.
Synthesis Vivado Synthesis
Support
Provided by Xilinx at the Xilinx Support web page
Notes:
1. For a complete list of supported devices, see the Vivado
IP catalog.
2. Contains a few Verilog files. Top level is VHDL.
3. Standalone driver information can be found in the
Software Developers Kit (SDK) installation directory. See
xilinx_drivers.htm in
<install_directory>/SDK/<release>/data/embeddedsw/
doc/xilinx_drivers.htm. Linux OS and driver support
information is available from
the Xilinx Wiki page.
4. For the supported versions of the tools, see the
Xilinx Design Tools: Release Notes Guide
.
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AXI VDMA v6.2 5
PG020 November 30, 2016
www.xilinx.com
Chapter 1
Overview
Many video applications require frame buffers to handle frame rate changes or changes to
the image dimensions (scaling or cropping). The AXI VDMA is designed to allow for efficient
high-bandwidth access between the AXI4-Stream video interface and the AXI4 interface.
Figure 1-1 illustrates the AXI VDMA Block Diagram.
After registers are programmed through the AXI4-Lite interface, Control/ Status logic block
generates appropriate commands to the DataMover to initiate Write and Read commands
on the AXI4 Master interface.
A configurable asynchronous line buffer is used to temporarily hold the pixel data prior to
writing it out to the AXI4-Memory Map interface or the AXI4-Stream interface.
In the Write path, the AXI VDMA accepts frames on the AXI4-Stream Slave interface and
writes it to system memory using the AXI4 Master interface.
In the Read path, the AXI VDMA uses the AXI4 Master interface for reading frames from
system memory and outputs it on the AXI4-Stream Master interface.
Both write and read paths operate independently. The AXI VDMA also provides an option to
synchronize the incoming/outgoing frames with an external synchronization signal.
X-Ref Target - Figure 1-1
Figure 1‐1: AXI VDMA Block Diagram
AXI4-Lite
AXI4-Stream
Registers
DataMover Line Buffer
Control and
Status
X13213
AXI4 Memory Map
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