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K7A801800M 256Kx36 & 512Kx18 Synchronous SRAM
- 1 -
Rev 6.0
March 2000
K7A803600M
Document Title
256Kx36 & 512Kx18-Bit Synchronous Pipelined Burst SRAM
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
Revision History
Rev. No.
0.0
0.1
0.2
0.3
0.4
0.5
0.6
1.0
2.0
3.0
4.0
5.0
6.0
Remark
Preliminary
Preliminary
Preliminary
Preliminary
Preliminary
Preliminary
Preliminary
Final
Final
Final
Final
Final
Final
History
Initial draft
Modify DC characteristics( Input Leakage Current test Conditions)
form VDD=VSS to VDD to Max.
Change DC Characteristics.
ISB value from 80mA to 130mA at -16
ISB value from 70mA to 120mA at -15
ISB value from 65mA to 110mA at -14
ISB value from 50mA to 100mA at -10
ISB1 value from 10mA to 30mA
ISB2 value from 10mA to 30mA
1. Remove speed bin -16.
2. Changed DC condition at Icc and parameters
Icc ; from 400mA to 420mA at -15,
from 375mA to 400mA at -14,
from 300mA to 350mA at -10,
ISB ; from 120mA to 150mA at -15,
from 110mA to 130mA at -14,
from 100mA to 120mA at -10,
1. ADD x32 organization.
1. ADD VDDQ Supply voltage( 2.5V I/O )
1. Changed VOL Max value from 0.2V to 0.4V at 2.5V I/O.
1. Final spec Release.
2. Remove x32 organization.
1. Remove VDDQ Supply voltage( 2.5V I/O )
1. Add VDDQ Supply voltage( 2.5V I/O )
1. Change tOE from 4.0ns to 3.8ns at -14 .
1. Add tCYC 167MHz and 200MHz.
2. Changed DC condition at Icc and parameters
Icc ; from 420mA to 400mA at -15,
from 400mA to 350mA at -14,
from 350mA to 300mA at -10,
1. Change tCD from 4.0ns to 3.8ns at -14 .
Draft Date
April. 10 . 1998
June .08. 1998
Aug . 27. 1998
Sep. 09. 1998
Oct. 15. 1998
Dec. 10. 1998
Dec. 23. 1998
Jan. 29. 1999
Feb. 25. 1999
May. 13. 1999
July. 05. 1999
Nov. 19. 1999
March 14. 2000
K7A801800M 256Kx36 & 512Kx18 Synchronous SRAM
- 2 -
Rev 6.0
March 2000
K7A803600M
256Kx36 & 512Kx18-bit Synchronous Pipelined Burst SRAM
The K7A803600M and K7A801800M are 9,437,184-bit Syn-
chronous Static Random Access Memory designed for high
performance second level cache of Pentium and Power PC
based System.
It is organized as 256K(512K) words of 36(18) bits and inte-
grates address and control registers, a 2-bit burst address
counter and added some new functions for high perfor-
mance cache RAM applications; GW, BW, LBO, ZZ. Write
cycles are internally self-timed and synchronous.
Full bus-width write is done by GW, and each byte write is
performed by the combination of WEx and BW when GW is
high. And with CS1 high, ADSP is blocked to control signals.
Burst cycle can be initiated with either the address status
processor(ADSP) or address status cache controller(ADSC)
inputs. Subsequent burst addresses are generated inter-
nally in the system′s burst sequence and are controlled by
the burst address advance(ADV) input.
LBO pin is DC operated and determines burst sequence(lin-
ear or interleaved).
ZZ pin controls Power Down State and reduces Stand-by
current regardless of CLK.
The K7A803600M and K7A801800M are fabricated using
SAMSUNG′s high performance CMOS technology and is
available in a 100pin TQFP and 119BGA package. Multiple
power and ground pins are utilized to minimize ground
bounce.
GENERAL DESCRIPTIONFEATURES
LOGIC BLOCK DIAGRAM
• Synchronous Operation.
• 2 Stage Pipelined operation with 4 Burst.
• On-Chip Address Counter.
• Self-Timed Write Cycle.
• On-Chip Address and Control Registers.
• 3.3V+0.165V/-0.165V Power Supply.
• I/O Supply Voltage 3.3V+0.165V/-0.165V for 3.3V I/O
or 2.5V+0.4V/-0.125V for 2.5V I/O
• 5V Tolerant Inputs Except I/O Pins.
• Byte Writable Function.
• Global Write Enable Controls a full bus-width write.
• Power Down State via ZZ Signal.
• LBO Pin allows a choice of either a interleaved burst or a linear
burst.
• Three Chip Enables for simple depth expansion with No Data
Contention only for TQFP ; 2cycle Enable, 1cycle Disable.
• Asynchronous Output Enable Control.
• ADSP, ADSC, ADV Burst Control Pins.
• TTL-Level Three-State Output.
• 100-TQFP-1420A / 119BGA(7x17 Ball Grid Array Package)
CLK
LBO
ADV
ADSC
ADSP
CS
1
CS
2
CS
2
GW
BW
WEx
OE
ZZ
DQa
0
~ DQd
7
or DQa0 ~ DQb7
BURST CONTROL
LOGIC
BURST
256Kx36 , 512Kx18
ADDRESS
CONTROL
OUTPUT
DATA-IN
ADDRESS
COUNTER
MEMORY
ARRAY
REGISTER
REGISTER
BUFFER
LOGIC
CONTROL
REGISTER
CONTROL
REGISTER
A
′
0
~A
′
1
A
0
~A
1
or A
2
~A
18
or A
0
~A
18
REGISTER
FAST ACCESS TIMES
PARAMETER Symbol -20 -16 -15 -14 -10 Unit
Cycle Time tCYC 5.0 6.0 6.7 7.2 10 ns
Clock Access Time tCD 3.1 3.5 3.8 3.8 4.5 ns
Output Enable Access Time tOE 3.1 3.5 3.8 3.8 4.5 ns
DQPa ~ DQPd
A
0
~A
17
A
2
~A
17
(x=a,b,c,d or a,b)
DQPa,DQPb
K7A801800M 256Kx36 & 512Kx18 Synchronous SRAM
- 3 -
Rev 6.0
March 2000
K7A803600M
PIN CONFIGURATION(TOP VIEW)
PIN NAME
Notes : 1. A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
2. The pin 42 is reserved for address bit for the 16Mb .
SYMBOL PIN NAME TQFP PIN NO. SYMBOL PIN NAME TQFP PIN NO.
A0 - A17
ADV
ADSP
ADSC
CLK
CS1
CS2
CS2
WEx(x=a,b,c,d)
OE
GW
BW
ZZ
LBO
Address Inputs
Burst Address Advance
Address Status Processor
Address Status Controller
Clock
Chip Select
Chip Select
Chip Select
Byte Write Inputs
Output Enable
Global Write Enable
Byte Write Enable
Power Down Input
Burst Mode Control
32,33,34,35,36,37,43
44,45,46,47,48,49,50
81,82,99,100
83
84
85
89
98
97
92
93,94,95,96
86
88
87
64
31
VDD
VSS
N.C.
DQa0~a7
DQb0~b7
DQc0~c7
DQd0~d7
DQPa~Pd
VDDQ
VSSQ
Power Supply(+3.3V)
Ground
No Connect
Data Inputs/Outputs
Output Power Supply
(2.5V or 3.3V)
Output Ground
15,41,65,91
17,40,67,90
14,16,38,39,42,66
52,53,56,57,58,59,62,63
68,69,72,73,74,75,78,79
2,3,6,7,8,9,12,13
18,19,22,23,24,25,28,29
51,80,1,30
4,11,20,27,54,61,70,77
5,10,21,26,55,60,71,76
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100 Pin TQFP
(20mm x 14mm)
DQPc
DQc0
DQc1
VDDQ
VSSQ
DQc2
DQc3
DQc4
DQc5
VSSQ
VDDQ
DQc6
DQc7
N.C.
VDD
N.C.
VSS
DQd0
DQd1
VDDQ
VSSQ
DQd2
DQd3
DQd4
DQd5
VSSQ
VDDQ
DQd6
DQd7
DQPd
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQPb
DQb7
DQb6
VDDQ
VSSQ
DQb5
DQb4
DQb3
DQb2
VSSQ
VDDQ
DQb1
DQb0
VSS
N.C.
VDD
ZZ
DQa7
DQa6
VDDQ
VSSQ
DQa5
DQa4
DQa3
DQa2
VSSQ
VDDQ
DQa1
DQa0
DQPa
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
A6
A7
CS1
CS2
WEd
WEc
WEb
WEa
CS2
VDD
VSS
CLK
GW
BW
OE
ADSC
ADSP
ADV
A8
81
A9
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
A15
A14
A13
A12
A11
A10
A17
N.C.
VDD
VSS
N.C.
N.C.
A0
A1
A2
A3
A4
A5
31
LBO
A16
K7A803600M(256Kx36)
K7A801800M 256Kx36 & 512Kx18 Synchronous SRAM
- 4 -
Rev 6.0
March 2000
K7A803600M
PIN CONFIGURATION(TOP VIEW)
PIN NAME
Notes : 1. A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
2. The pin 42 is reserved for address bit for the 16Mb .
SYMBOL PIN NAME TQFP PIN NO. SYMBOL PIN NAME TQFP PIN NO.
A0 - A18
ADV
ADSP
ADSC
CLK
CS1
CS2
CS2
WEx
OE
GW
BW
ZZ
LBO
Address Inputs
Burst Address Advance
Address Status Processor
Address Status Controller
Clock
Chip Select
Chip Select
Chip Select
Byte Write Inputs
Output Enable
Global Write Enable
Byte Write Enable
Power Down Input
Burst Mode Control
32,33,34,35,36,37,43
44,45,46,47,48,49,50
80,81,82,99,100
83
84
85
89
98
97
92
93,94
86
88
87
64
31
VDD
VSS
N.C.
DQa0 ~ a7
DQb0 ~ b7
DQPa, Pb
VDDQ
VSSQ
Power Supply(+3.3V)
Ground
No Connect
Data Inputs/Outputs
Output Power Supply
(2.5V or 3.3V)
Output Ground
15,41,65,91
17,40,67,90
1,2,3,6,7,14,16,25,28,29,
30,38,39,42,51,52,53,56,
57,66,75,78,79,95,96
58,59,62,63,68,69,72,73
8,9,12,13,18,19,22,23
74,24
4,11,20,27,54,61,70,77
5,10,21,26,55,60,71,76
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100 Pin TQFP
N.C.
N.C.
N.C.
VDDQ
VSSQ
N.C.
N.C.
DQb0
DQb1
VSSQ
VDDQ
DQb2
DQb3
N.C.
VDD
N.C.
VSS
DQb4
DQb5
VDDQ
VSSQ
DQb6
DQb7
DQPb
N.C.
VSSQ
VDDQ
N.C.
N.C.
N.C.
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
N.C.
N.C.
VDDQ
VSSQ
N.C.
DQPa
DQa7
DQa6
VSSQ
VDDQ
DQa5
DQa4
VSS
N.C.
VDD
ZZ
DQa3
DQa2
VDDQ
VSSQ
DQa1
DQa0
N.C.
N.C.
VSSQ
VDDQ
N.C.
N.C.
N.C.
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
A6
A7
CS1
CS2
N.C.
N.C.
WEb
WEa
CS2
VDD
VSS
CLK
GW
BW
OE
ADSC
ADSP
ADV
A8
81
A9
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
A15
A14
A13
A12
A11
A18
N.C.
VDD
VSS
N.C.
N.C.
A0
A1
A2
A3
A4
A5
31
LBO
A16
K7A801800M(512Kx18)
A17
A10
(20mm x 14mm)
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