SAMSUNG-K7K3218T2C.pdf

1Mx36 & 2Mx18 DDRII+ CIO b2 SRAM

K7K3236T2C

K7K3218T2C

- 1 -

Rev. 1.3 August 2008

36Mb DDRII+ SRAM Specification

* Samsung Electronics reserves the right to change products or specification without notice.

INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,

AND IS SUBJECT TO CHANGE WITHOUT NOTICE.

1Mx36 & 2Mx18 DDRII+ CIO b2 SRAM

K7K3236T2C

K7K3218T2C

- 2 -

Rev. 1.3 August 2008

Remark

Advance

Preliminary

Preliminary

Final

Final

History

tance

1. Correct typo

1. Change ICC measure condition

2. Change programmable impedence output buffer operation

3. Add AC Timing Characteristics

1. Delete AC/DC Parameter of 450MHz

Dec. 12, 2005

Jan. 30, 2007

1Mx36 & 2Mx18 DDRII+ CIO b2 SRAM

K7K3236T2C

K7K3218T2C

- 3 -

Rev. 1.3 August 2008

• 1.8V+0.1V/-0.1V Power Supply.

• DLL circuitry for wide output data valid window and future

• I/O Supply Voltage 1.5V+0.1V/-0.1V

• Registered address, control and data input/output.

• DDR(Double Data Rate) Interface on read and write ports.

• Fixed 2-bit burst for both read and write operation.

• Clock-stop supports to reduce current.

• Two input clocks(K and K

• Two echo clocks (CQ and CQ

LD

ADDRESS

R/W

Doff

K

K

BWX

WRITE/READ DECODE

72

CQ, CQ

K7K3236T2C-F(E)C(I)33 3.0 0.45 ns

K7K3218T2C-F(E)C(I)33 3.0 0.45 ns

QVLD

1Mx36 & 2Mx18 DDRII+ CIO b2 SRAM

K7K3236T2C

K7K3218T2C

- 4 -

Rev. 1.3 August 2008