JEDEC
PUBLICATION
ADAPTER TEST BOARD
RELIABILITY TEST GUIDELINES
JEP176
JANUARY 2018
JEDEC SOLID STATE TECHNOLOGY ASSOCIATION
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JEDEC Publication No. 176
-i-
ADAPTER TEST BOARD RELIABILITY TEST GUIDELINES FOR INTEGRATED
CIRCUITS
CONTENTS
Introduction 1
1 Scope 2
2 Terms and definitions 2
3 Reference documents 3
4 General requirements 5
4.1 Objective 5
4.2 Stress/test parameters 5
4.3 Electrical Test 5
5 Adapter test board design 5
6 Recommended reliability tests 7
6.1 General tests 7
6.2 Mounting IC components on adapter test boards & preconditioning recommendations 7
6.3 Temperature cycling (TC) recommendations 8
6.4 Highly accelerated stress test recommendations 9
6.5 High temperature storage life recommendations 9
6.6 High temperature operation life recommendations
6.7 Non-volatile memory endurance cycling and data retention recommendations
9
9
6.8 Failure analysis recommendations 10
Annex A (informative) Examples of adapter test board designs 11
Annex B (informative) Optical inspection criteria 15
JEDEC Publication No. 176
-ii-
Introduction
Traditionally, integrated circuits packaged in through-hole packages and surface mount packages
can be placed directly into Automatic Test Equipment (ATE) for electrical test for reliability
tests and production. However, for solder-bump-based packages, this test method becomes
challenging. One alternative method of performing electrical tests and reliability tests is to
mount integrated circuits in solder bump-based-packages onto adapter test boards, which enables
the connection between the integrated circuit devices to the biased reliability boards and ATE.
Chip-Scale Packages (CSP), Flip-Chip Die that are to be assembled directly to boards, and other
Fine-Pitch Packages (FPP) may benefit from use of an electrical test adapter board for
component-level reliability testing.
This document provides guidelines on testing of integrated circuit devices mounted on adapter
test boards specifically for the purpose of performing reliability tests to identify component-level
failure mechanisms. The use of adapter test boards is a lower cost alternative to using custom
sockets on the biased reliability boards and ATE interface boards.
This publication recommends that JESD47 or another JEDEC qualification standard be used.
This document augments those requirements with guidance on some testing that may be
preferable to execute in a format where the supplied device is mounted on an adapter test board
either for the purpose of handling efficiency through the reliability stress or electrical test
evaluations. The reliability stress test is performed to assess the robustness of the chip-scale,
flip-chip, and fine-pitch package manufacturing process and/or to determine whether there are
chip-package interaction effects. These considerations apply to devices in chip-scale packaging,
flip-chip direct attach, and fine-pitch packages. This document also offers guidelines for
mitigating the risk of adapter test-board-related failure mechanisms.
JEDEC Publication No. 176
Page 1
ADAPTER TEST BOARD RELIABILITY TEST GUIDELINES
(From JEDEC Board Ballot JCB-17-36, formulated under the cognizance of the JC-14.3 Subcommittee
on Silicon Devices Reliability Qualification and Monitoring.)
1 Scope
This publication describes guidelines for applying JEDEC reliability tests and recommended
testing procedures to integrated circuits that require adapter test boards for electrical and
reliability testing. These tests are used frequently in qualifying integrated circuits as a new
product, a product family, or as products in a process which is being changed.
Integrated circuit devices in various packages that cannot be tested directly with the Automated
Test Equipment (ATE) are each mounted on an adapter test board for testing. Some common
devices mounted on adapter test boards for test purposes are Chip-Scale Package, Flip-Chip Die,
and Fine-Pitch Package devices (e.g., 64-Lead QFN package with 0.50-mil lead pitch).
This document provides guidelines for adapter test board-level reliability tests, recommended
testing procedures, test board designs, and construction materials. It is aimed to provide a
reproducible assessment of the reliability performance of integrated circuit devices while
duplicating the failure modes normally observed during product life cycle. The reliability test
recommendations do not apply to the following:
a) Integrated circuits that are stressed and/or tested in an electrical socket.
b) WLCSP devices that are stressed and/or tested using a wafer-level probe card.
c) Second-level solder joint reliability tests such as drop test, thermal cycle test, bend test, etc.
These reliability tests are capable of evaluating and simulating package and device failures in an
accelerated manner compared to use conditions. The guidelines prescribed in this publication are
not aimed for reliability tests for devices in extreme use conditions such as military applications,
automotive under-the-hood applications, or uncontrolled avionics environments. Each reliability
test should be examined for:
a) Any potential new and unique failure mechanisms,
b) Any situation where these tests and/or conditions may induce false failures.
