JEDEC
PUBLICATION
FOUNDRY PROCESS
QUALIFICATION GUIDELINES –
BACKEND OF LINE
(Wafer Fabrication Manufacturing Sites)
JEP001-1A
(Revision of JEP001A, February 2014)
SEPTEMBER 2018
JEDEC SOLID STATE TECHNOLOGY ASSOCIATION
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JEDEC Publication No. 001-1A
-i-
FOUNDRY PROCESS QUALIFICATION GUIDELINES – BACKEND OF LINE
(Wafer Fabrication Manufacturing Sites)
Contents
Page
Foreword
ii
Introduction
ii
Acronyms
iii
1
Scope
1
2
Quality system
1
3
Responsibilities
1
3.1
Level 1 qualification
1
3.2
Level 2 qualification
2
3.3
Reporting Requirements
2
4
Sample size
2
5
Use of packages
2
6
Reference documents
3
6.1
Industry standard documents
3
6.2
Selected references
4
7
Qualification test summary table
4
8
Interconnect reliability
5
8.1
Electromigration
5
8.2
Stress migration
8
8.3
Thermal cycling (copper interconnect)
10
8.4
Inter/intra-metal dielectric integrity
11
8.5
Yield reporting
13
8.6
Report requirements
14
9
Construction analysis
14
Annex A
Differences between revisions
16
JEDEC Publication No. 001-1A
-ii-
Foreword
The publication is divided into three parts, backend of line (JEP001-1A), transistor level (JEP001-2A), and
product level testing (JEP001-3A). The document provides methodologies for the minimum set of
measurements to qualify a new semiconductor wafer process. It is written with particular reference to a
generic silicon based CMOS logic technology. While it may be applicable to other technologies (e.g., analog
CMOS, bipolar, BICMOS, GaAs, etc.), some sections apply specifically to CMOS. No effort was made in the
present document to cover all the qualification requirements for specific other technologies, e.g., Cu/Low K
interconnects or ultra-thin gate oxide.
Any qualification requirements beyond the minimum set are to be developed for the specific performance
expected of the technology. The minimum set of measurements and the requirements for the qualification
based on those measurements are to be determined between the foundry and its customers on an
individual basis The process technology owner (foundry) will be required to document the details of specific
testing unique to the process being qualified.
The guideline documents common best practices in the semiconductor industry and updated in accordance
to advancement in the semiconductor industry and JEDEC bylaws of periodic reviews.
Introduction
This publication, was originally published as JP-001 entitled 'Foundry Process Qualification Guidelines', it
was co-sponsored by JEDEC and the FSA (Fabless Semiconductor Association). It originated at the FSA
as a technology specific document, and has evolved into a generic set of qualification methodologies. The
JEDEC sponsoring committee is JC-14 through its JC-14.2 subcommittee on wafer level reliability.
This document encompasses and references a number of other standards and procedures, some of which
are in a state of constant revision and update. While a case might be made for producing a lean, concise
guideline that does not spell out specific procedures or requirements, the proposition of spelling out the
essence of a comprehensive set of methodologies in one place has a practical value that outweighs the
case for simplicity.(comment : the requirements are only spelled out in a number of cases. Best to be
consistent and let the existing JEDEC specs speak for themselves)
This publication is split into three parts: JEP001-1A, JEP001-2A, and JEP001-3A as described
below. It is intended that each part references the appropriate test and requirement noting that
some tests may be performed on the package level. This standard should be read alongside
reliability requirements established between the supplier and customer.
The structure of the JEDEC JEP001 series as currently conceived is as follows:
Part 1 – Backend of line testing
Part 2 – Transistor-level testing
Part 3 – Product-level testing
JEDEC Publication No. 001-1A
-iii-
Acronyms
The following acronyms have been used in this document:
WLR: wafer level reliability
EM: electromigration
SM: stress migration/voiding
IMD: inter/intra-metal dielectric
VRDB: voltage ramp dielectric breakdown
TDDB: time-dependent dielectric breakdown
QBD: Charge to breakdown
TVS: triangular voltage sweep
HTOL: high temperature operating life
EFR: early failure rate
FIT: Failures in time
THB: temperature-humidity bias
HAST: highly-accelerated stress test
ESD: electrostatic discharge
TQV: technology qualification vehicle
PCM: process control monitor
FA: failure analysis
TC: temperature cycling
