JEDEC
PUBLICATION
Guidelines for GaAs MMIC
PHEMT/MESFET and HBT Reliability
Accelerated Life Testing
JEP118A
(Revision of JEP118, January 1993)
DECEMBER 2018
JEDEC SOLID STATE TECHNOLOGY ASSOCIATION
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JEDEC Publication No. 118A
-i-
Guidelines for GaAs MMIC PHEMT/MESFET and HBT Reliability Accelerated Life Testing
Contents
Page
Introduction ii
1 Scope 1
2 Related documents 1
3 Sample, selection and screening 1
4 Life tests 2
4.1 Electrical and Thermal Characterization 2
4.2 Step Stress Tests 4
4.3 Choice of Ambient Temperatures and other Operating Conditions 4
4.4 Electrical Stress 5
4.5 Sample Size 6
4.6 Failure Criteria 6
4.7 Data Taking 7
4.8 Failure Analysis 8
4.9 Data Analysis 8
4.10 Activation Energy and Extrapolated Lifetime 10
5 Reportable data 11
5.1 Devices 11
5.2 Stresses 11
5.3 Analysis 11
6 References 11
Annex A Statistical methods 12
Annex B Example of a life test 14
JEDEC Publication No. 118A
-ii-
Introduction
These guidelines apply to GaAs Monolithic Microwave Integrated Circuits (MMICs) and their individual
component building blocks, such as GaAs Metal-Semiconductor Field Effect Transistors (MESFETs),
Pseudomorphic High Electron Mobility Transistors (PHEMTs), Heterojunction Bipolar Transistors
(HBTs), resistors, and capacitors. While the procedure described in this document may be applied to
other semiconductor technologies, especially those used in RF and microwave frequency analog
applications, it is primarily intended for technologies based on GaAs and related III-V material systems
(InP, AlGaAs, InGaAs, InGaP, GaN, etc).
The objective of the tests described here is to estimate the expected wear-out lifetime of the devices at
operational temperatures and normal electrical bias conditions; usually the median lifetime (50% failure)
is projected for this purpose. The standard method for predicting device lifetime, where this value is too
large (many years) to be measured directly, is to run a series of accelerated life tests. Generally, only one
parameter, usually the device ambient temperature, is varied. A lifetime distribution is obtained at each
stressed temperature. These values are then fit to an acceleration model and extrapolated to the
temperature of interest. In other cases, the objective may be simply to determine the lifetime at a given
temperature.
The purpose of this document is to define a standard approach for evaluating the expected life of GaAs
MMICs so that results from different life tests can be compared, and so that a user of MMICs can predict
a lifetime for a specific application. It is assumed in the wording of this document that the MMIC
contains at least one FET or HBT, but the use of this document has no such limitations. Furthermore, the
wording suggests that the failures occur at the transistor; if this is not the case, then the stresses, tests and
failure criteria need to be re-evaluated to ensure that they are appropriate to the failing component.
To perform the life tests, a sample of devices is selected and subjected to a stress in excess of normal use
conditions to accelerate the failure or to decrease the lifetime. The devices used can be MMICs.
Alternatively, the lifetime of MMICs can be determined by determining the failure rate vs. time of
component structures within the MMIC, e.g., FETs, PHEMTs, HBTs, resistors, capacitors and bond
wires, given the structure and temperature profile of a MMIC. This latter calculation is not a
straightforward one and a specific procedure is not addressed in this document. If it is assumed that the
failure mechanisms are independent, the percentage of MMICs surviving to a given time is the product of
the percentages of survival of each component.
Conducting accelerated tests of these devices can be very difficult because of the complexity of
determining the channel temperature Tc in the PHEMT or junction temperature Tj in the HBT, the high
cost of large sample sizes (especially where radio frequency (RF) stressing is performed), the possible
device damages by EOS or mishandling during the multiple measurements, and the need to extrapolate to
the temperatures of actual device use. In particular, any difference in the techniques for determining the
device thermal resistance that results even in a small change of the thermal resistance value may have
substantial impact on the corresponding predicted failure rate. For example, every 10C increase in
channel temperature would result in a factor of 1.5 to 3 in device lifetime reduction for activation energy
of 1 eV according to Arrhenius model. The task of standardizing a method for determining channel or
junction temperature is not addressed by this document; however, whichever technique is used should be
documented and described in any resulting life test report.
JEDEC Publication No. 118A
Page 1
Guidlines for GaAs PHEMT/MESFET and HBT Reliability Accelerated Life Testing
(From JEDEC Board Ballot JCB-18-35, formulated under the cognizance of JC-14.7 Subcommittee on Gallium
Arsenide Reliability and Quality Standards.)
1 Scope
Life tests are run for various purposes. Tests run to detect the level of infant mortality involve short time
duration; unless the percentage of devices having infant mortality is extremely high, the sample size
specified in this document is not nearly sufficient. Tests to determine device lifetime for a specific
application may be conducted by or for a customer; here the stress and test conditions may be specific to
the application. Other life tests are run by a manufacturer and are concerned with determining the lifetime
of devices under typical or extreme operation.
It is assumed that a given MMIC product is designated either as a power, general purpose, or low-noise
(small signal) device, based on the intended use of the product. For low-noise devices and passive
components, the RF voltage levels are small enough that it may be possible to simulate the stress
accurately by imposing only DC bias.
This document applies both to packaged and unpackaged devices. Where the devices are bare die or in
packages not suitable for stressing at high temperature, additional failures may occur due to the
packaging, which are not considered part of the product being tested. If this occurs, such failures should
be excluded from the population when calculating predicted failure rate.
Since it is unlikely that every structure and failure mechanism in a MMIC is known when these guidelines
are written, some judgment must be used in applying the principles of this document to the specific tests.
Where an unusual circumstance forces exceptions to these guidelines, the exception shall be stated in the
life test report.
2 Related documents
JESD91, Method for Developing Acceleration Models for Electronic Component Failure Mechanisms
JESD226, RF Biased Life (RFBL) Test
