FPGA设计信号上升沿、下降沿、双边沿检测verilog源代码+测试激励Testbench文件.zip

FPGA设计信号上升沿、下降沿、双边沿检测verilog源代码+测试激励Testbench文件： module edge_detector_tb () ; reg clk; reg rst_n; reg din; wire up_edge; wire down_edge; wire both_edge; edge_detector u_edge_detector( .clk (clk), .rst_n (rst_n), .din (din), .up_edge (up_edge), .down_edge (down_edge), .both_edge (both_edge)); always #5 clk = ~clk; initial begin clk = 0; rst_n = 1; din = 0; #5 rst_n = 0; #5 rst_n = 1; #10 din = 1; #20 din = 0; #40 $stop; end