FPGA计数器开发 格雷码、环形、约翰逊计数器、FLSR、简易数字秒表设计verilog源码+测试激励Testbench文件

FPGA计数器开发 格雷码、环形、约翰逊计数器、FLSR、简易数字秒表设计verilog源码+测试激励Testbench文件： module count_bin02_tb(); reg clk; reg rst_n; reg mode; wire [3:0] number; wire zero; count_bin02 u_count_bin02( .clk (clk), .rst_n (rst_n), .mode (mode), .number (number), .zero (zero) ); always #5 clk =~ clk; initial begin clk = 0; mode = 1; #5 rst_n = 1; #5 rst_n = 0; #5 rst_n = 1; #150 mode = 0; #1000; $finish; end