DS1302Z读取和设置RTC时间显示在数码管cyclone2 FPGA实验Verilog源码Quartus9.0工程文件

+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Legal Partition Candidates ; +--------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ ; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ; +--------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ ; LED_NUMBER ; 66 ; 43 ; 0 ; 43 ; 16 ; 43 ; 43 ; 43 ; 0 ; 0 ; 0 ; 0 ; 0 ; ; I_RTC_WR_CTL ; 18 ; 0 ; 0 ; 0 ; 11 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; +--------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+