RTC实时时钟[DS1302Z]读写实验例程 cyclone2 FPGA实验Verilog源码Quartus9.0工程文件
DS1302_APP I_DS1302_APP
(
.RST_B (RST_B ),
.SYSCLK (SYSCLK ),
.RTC_RST (RTC_RST ),
.RTC_CLK (RTC_CLK ),
.RTC_IO (RTC_IO ),
.TUBE_SEL (TUBE_SEL ),
.TUBE_DATA (TUBE_DATA )
);
//Clock
always #10 SYSCLK = ~ SYSCLK;
initial
begin
#0 SYSCLK = 0;
RST_B = 0;
#35 RST_B = 1;
end
endmodule
