################################################################################
# Vivado (TM) v2017.4 (64-bit)
#
# README.txt: Please read the sections below to understand the steps required
# to simulate the design for a simulator, the directory structure
# and the generated exported files.
#
################################################################################
1. Simulate Design
To simulate design, cd to the simulator directory and execute the script.
For example:-
% cd questa
% ./top.sh
The export simulation flow requires the Xilinx pre-compiled simulation library
components for the target simulator. These components are referred using the
'-lib_map_path' switch. If this switch is specified, then the export simulation
will automatically set this library path in the generated script and update,
copy the simulator setup file(s) in the exported directory.
If '-lib_map_path' is not specified, then the pre-compiled simulation library
information will not be included in the exported scripts and that may cause
simulation errors when running this script. Alternatively, you can provide the
library information using this switch while executing the generated script.
For example:-
% ./top.sh -lib_map_path /design/questa/clibs
Please refer to the generated script header 'Prerequisite' section for more details.
2. Directory Structure
By default, if the -directory switch is not specified, export_simulation will
create the following directory structure:-
<current_working_directory>/export_sim/<simulator>
For example, if the current working directory is /tmp/test, export_simulation
will create the following directory path:-
/tmp/test/export_sim/questa
If -directory switch is specified, export_simulation will create a simulator
sub-directory under the specified directory path.
For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim'
command will create the following directory:-
/tmp/test/my_test_area/func_sim/questa
By default, if -simulator is not specified, export_simulation will create a
simulator sub-directory for each simulator and export the files for each simulator
in this sub-directory respectively.
IMPORTANT: Please note that the simulation library path must be specified manually
in the generated script for the respective simulator. Please refer to the generated
script header 'Prerequisite' section for more details.
3. Exported script and files
Export simulation will create the driver shell script, setup files and copy the
design sources in the output directory path.
By default, when the -script_name switch is not specified, export_simulation will
create the following script name:-
<simulation_top>.sh (Unix)
When exporting the files for an IP using the -of_objects switch, export_simulation
will create the following script name:-
<ip-name>.sh (Unix)
Export simulation will create the setup files for the target simulator specified
with the -simulator switch.
For example, if the target simulator is "ies", export_simulation will create the
'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib'
file.
没有合适的资源?快使用搜索试试~ 我知道了~
温馨提示
1、FPGA --- XILINX ; 2、DDR4 ---MT40A512M16; 3、DDR4读写测试已经验证完成,功能正常。 4、开发环境:vivado18.3;
资源推荐
资源详情
资源评论
收起资源包目录
xilinx FPGA verilog DDR4测试工程 (1206个子文件)
xsim.ini.bak 19KB
elaborate.bat 1KB
compile.bat 1KB
simulate.bat 804B
runme.bat 229B
runme.bat 229B
runme.bat 229B
runme.bat 229B
runme.bat 229B
runme.bat 229B
bd_9054.bd 26KB
bd_9054.bd 26KB
top.bit 4.64MB
bd_9054.bmm 730B
bd_9054.bmm 730B
bd_9054.bxml 7KB
bd_9054.bxml 7KB
xsim_9.c 704KB
xsim.dbg 2.48MB
top_routed.dcp 21.82MB
top_placed.dcp 16.99MB
top_opt.dcp 12.14MB
ddr4_0.dcp 10.43MB
ddr4_0.dcp 10.43MB
ddr4_0.dcp 10.43MB
ddr4_0.dcp 10.41MB
ddr4_0.dcp 10.38MB
ddr4_0_phy.dcp 2.51MB
ila_1.dcp 1.44MB
ila_1.dcp 1.44MB
ila_1.dcp 1.44MB
ila_0.dcp 1.14MB
ila_0.dcp 1.14MB
ila_0.dcp 1.14MB
dbg_hub_CV.dcp 345KB
dbg_hub_CV.dcp 323KB
example_top.dcp 303KB
top.dcp 203KB
compile.do 15KB
compile.do 15KB
compile.do 15KB
compile.do 15KB
compile.do 15KB
compile.do 15KB
compile.do 14KB
compile.do 14KB
compile.do 1KB
compile.do 1KB
compile.do 1KB
compile.do 1KB
compile.do 1KB
compile.do 1KB
compile.do 1KB
compile.do 1KB
simulate.do 459B
simulate.do 459B
simulate.do 451B
simulate.do 451B
simulate.do 451B
simulate.do 451B
elaborate.do 349B
elaborate.do 349B
simulate.do 303B
simulate.do 303B
simulate.do 294B
simulate.do 294B
simulate.do 294B
simulate.do 294B
elaborate.do 193B
elaborate.do 193B
simulate.do 189B
simulate.do 189B
simulate.do 187B
simulate.do 187B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
simulate.do 11B
simulate.do 11B
simulate.do 11B
simulate.do 11B
calibration_ddr.elf 91KB
calibration_ddr.elf 91KB
mb_bootloop_le.elf 643B
mb_bootloop_le.elf 643B
mb_bootloop_le.elf 643B
mb_bootloop_le.elf 643B
共 1206 条
- 1
- 2
- 3
- 4
- 5
- 6
- 13
阿Q在学FPGA(WX-FD0427)
- 粉丝: 98
- 资源: 23
上传资源 快速赚钱
- 我的内容管理 展开
- 我的资源 快来上传第一个资源
- 我的收益 登录查看自己的收益
- 我的积分 登录查看自己的积分
- 我的C币 登录后查看C币余额
- 我的收藏
- 我的下载
- 下载帮助
安全验证
文档复制为VIP权益,开通VIP直接复制
信息提交成功
- 1
- 2
- 3
前往页